Showing 21 - 40 results of 105 for search 'Kuen-Jong Lee', query time: 0.11s Refine Results
  1. 21
    Bridging Fault Analysis and Logic Gate Threshold Voltage Determination
    by Duh, Wern-Yih, 杜文毅
    Published 1998
    Other Authors: “...Kuen-Jong Lee...”
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  2. 22
    Automatic synthesis of boundary scan and BIST architectures for digital and analog circuits
    by Sheng-Yih Jeng, 鄭昇益
    Published 1994
    Other Authors: “...Kuen-Jong Lee...”
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  3. 23
    Error Detection, Diagnosis, and Fault Tolerance for Analog Filters
    by Cheng-Hsuing Kuo, 郭政雄
    Published 1994
    Other Authors: “...Kuen-Jong Lee...”
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  4. 24
    Output Reduction and Data Compression for System-on-a-Chip
    by Chein-Wei Fang, 方建偉
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  5. 25
    Design and Test of Embedded Processors Based on ARM9 Structure
    by Tsuei-Ling Hsieh, 謝翠玲
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  6. 26
    Inside-Core Event-Trigger Mechanism for SoC Silicon Debugging
    by Jia-WeiJhou, 周佳緯
    Published 2012
    Other Authors: “...Kuen-Jong Lee...”
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  7. 27
    Efficient On-Chip Test Generation Scheme Based on Multiple Twisted-Ring Counters
    by Wee-LungAng, 洪偉倫
    Published 2012
    Other Authors: “...Kuen-Jong Lee...”
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  8. 28
    An Efficient Deadlock-Free Multicast Routing Approach for Mesh-Based Networks-on-Chip
    by Hung-YangYang, 楊鴻陽
    Published 2013
    Other Authors: “...Kuen-Jong Lee...”
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  9. 29
    An Efficient Deadlock-Free Communication Scheme for 3D NoC-Bus Hybrid Mesh Architecture
    by Shin-EnJian, 簡新恩
    Published 2013
    Other Authors: “...Kuen-Jong Lee...”
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  10. 30
    Data Invalidation Prevention in Silicon Debug for Multiple-Clock Systems
    by YuanChang, 張源
    Published 2013
    Other Authors: “...Kuen-Jong Lee...”
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  11. 31
    A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC
    by Hsin-ChenChen, 陳信辰
    Published 2013
    Other Authors: “...Kuen-Jong Lee...”
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  12. 32
    A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores
    by Si-Yuan Liang, 梁思遠
    Published 2008
    Other Authors: “...Kuen-Jong Lee...”
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  13. 33
    Fast Simulation and Architecture Reconfiguration of SoC Test Platform at Electronic System Level
    by Chih-yuan Hsiao, 蕭智元
    Published 2008
    Other Authors: “...Kuen-Jong Lee...”
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  14. 34
    The Counter-Based Output Selection Method with Unknown-Preventing Capability
    by Yu-Hua Wu, 吳育樺
    Published 2008
    Other Authors: “...Kuen-Jong Lee...”
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  15. 35
    A Low-Cost On-Chip SOC Debug Platform with On-Line Monitor Capability for System Bus and IP Cores
    by Shao-Yuan Chen, 陳紹元
    Published 2008
    Other Authors: “...Kuen-Jong Lee...”
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  16. 36
    IEEE 1500 Based On-Chip Delay Fault Testing
    by Yu-Hsien Cheng, 程育賢
    Published 2008
    Other Authors: “...Kuen-Jong Lee...”
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  17. 37
    An Efficient On-chip Network Interface for Standard Interface Protocol
    by Wen-HungHuang, 黃文鴻
    Published 2011
    Other Authors: “...Kuen-Jong Lee...”
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  18. 38
    An On-Chip Delay Test Architecture for Cores with Multiple-Clock Domains
    by Shih-HsiangDai, 戴士翔
    Published 2011
    Other Authors: “...Kuen-Jong Lee...”
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  19. 39
    An Output Selection Scheme for Test Response Compaction
    by Shih-HsunChien, 簡士勛
    Published 2011
    Other Authors: “...Kuen-Jong Lee...”
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  20. 40
    EPIDETOX: an ESL Platform for Integrated Circuit DEsign and TOol eXploration
    by I-JouChen, 陳伊柔
    Published 2011
    Other Authors: “...Kuen-Jong Lee...”
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