Showing 61 - 80 results of 105 for search 'Kuen-Jong Lee', query time: 0.10s Refine Results
  1. 61
    A General Power Management System
    by Chin-Yu Chen, 陳俊裕
    Published 1996
    Other Authors: “...Kuen-Jong Lee...”
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  2. 62
    A Current Mode testable and Diagnosable Design of OTA-C Filters
    by Kou-Sheng Huang, 黃國聲
    Published 1996
    Other Authors: “...Kuen-Jong Lee...”
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  3. 63
    A Gate-Level Schematic Generation System and Its Applications on Circuit Testing
    by Yu-Tsang Shieh, 謝雨蒼
    Published 1996
    Other Authors: “...Kuen-Jong Lee...”
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  4. 64
    High-Performance Component Design for SOC Test Platforms with Mixed-Signal Test Capability
    by Jian-Jhih You, 尤建智
    Published 2007
    Other Authors: “...Kuen-Jong Lee...”
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  5. 65
    Output-Selection-Based Response Compaction and Lower Bound on Observation Bits
    by Cheng-Pin Chiu, 邱政斌
    Published 2007
    Other Authors: “...Kuen-Jong Lee...”
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  6. 66
    A Software-Based Test Methodology for Direct-Mapped Data Cache
    by Cheng-Wei Yen, 顏成偉
    Published 2007
    Other Authors: “...Kuen-Jong Lee...”
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  7. 67
    A Framework for Electronic System Level (ESL) Test Platform
    by Chia-te Wang, 王嘉德
    Published 2007
    Other Authors: “...Kuen-jong Lee...”
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  8. 68
    Diagnosis Pattern Generation to Distinguish Transition Fault and Stuck-Open Faults in CMOS Logic Circuits
    by Sheng-TzeWang, 王聖澤
    Published 2015
    Other Authors: “...Kuen-Jong Lee...”
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  9. 69
    Theory and Applications of Error-Tolerance Techniques for Effective Yield Improvement
    by Tong-Yu Hsieh, 謝東佑
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  10. 70
    Transaction Level Modeling of the High Performance Bus Design with OCP Interface
    by Yi-jiun Chang, 張怡均
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  11. 71
    A Low-Cost On-Chip SOC Debug Platform with Multiple Clock Domain Breakpoint Insertion Capabilities
    by Chi-Hung Yao, 姚奇宏
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  12. 72
    A Rotation-based BIST with Feedback Configurations
    by Chen-Tsung Tsai, 蔡振宗
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  13. 73
    A SoC Debug Platform with Inside-Core Adjustment and Event Trigger Capabilities
    by Shih-Hsing Hsieh, 謝仕興
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  14. 74
    On-Chip Delay Testing for Multiple ClockDomain Cores on SoC Test Platform
    by Ming-Ze Hung, 洪銘澤
    Published 2009
    Other Authors: “...Kuen-Jong Lee...”
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  15. 75
    On the Testing of Digital Filter Circuits
    by Jia-En Chuang, 莊佳恩
    Published 1999
    Other Authors: “...Kuen-Jong Lee...”
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  16. 76
    On the testing of Switched-Current Circuits
    by Kevin Chuang, 莊凱文
    Published 1999
    Other Authors: “...Kuen-Jong Lee...”
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  17. 77
    Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
    by Ing-Heng Shih, 石穎衡
    Published 1999
    Other Authors: “...Kuen-Jong Lee...”
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  18. 78
    Testable Design and Implementation of Operational Transconductance Amplifier-Capacitor Based Circuits
    by Wei-Chiang Wang, 王煒強
    Published 1999
    Other Authors: “...Kuen-Jong Lee...”
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  19. 79
    An Integrated System for Assigning Signal Flow Direction to CMOS Transistors
    by Chih Nan Wang, 王志男
    Published 1993
    Other Authors: “...Kuen Jong Lee...”
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  20. 80
    On the Design and Implementation of Embedded Memory Testing and Built-In Self-Test Schemes
    by Wei-Lun Wang, 王維倫
    Published 2001
    Other Authors: “...Kuen-Jong Lee...”
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