Showing 81 - 100 results of 105 for search 'Kuen-Jong Lee', query time: 0.19s Refine Results
  1. 81
    Low Power Testing for CMOS Logic Testing
    by Tsung-Chu Huang, 黃宗柱
    Published 2002
    Other Authors: “...Kuen-Jong Lee...”
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  2. 82
    Complete Debug Procedures for Realistic Industrial Applications Based on A Low-Cost On-Chip SoC Debug Platform
    by Chun-HanFang, 方俊翰
    Published 2010
    Other Authors: “...Kuen-Jong Lee...”
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  3. 83
    Design and Test of Platform-Based SOC with Advanced On-Chip Communication Architectures
    by Chin-YaoChang, 張欽堯
    Published 2013
    Other Authors: “...Kuen-Jong Lee...”
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  4. 84
    High Performance On-Chip Bus Design for Advanced Bus Protocols
    by Yu-ChiehLin, 林郁傑
    Published 2011
    Other Authors: “...Kuen-Jong Lee...”
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  5. 85
    Automatic Test Pattern Generation for CMOS Bridging Faults
    by Cheng-Liang Tsai, 蔡政良
    Published 1995
    Other Authors: “...Kuen-Jong Lee...”
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  6. 86
    A design and an automatic generation system for mixed-mode boundary scan with DC and AC testing capability
    by Tian-Poe Lee, 李天寶
    Published 1995
    Other Authors: “...Kuen-Jong Lee...”
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  7. 87
    Output Bit Selection Methodology for Test Response Compaction
    by Wei-ChengLien, 連唯証
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  8. 88
    An On-Chip Method for PLL jitter Measurement
    by Jer-Lun Hsu, 許哲綸
    Published 2002
    Other Authors: “...Kuen-Jong Lee...”
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  9. 89
    Test Scheduling for Core-Based SOC Design Under Multiple Constraints
    Other Authors: “...Kuen-Jong Lee...”
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  10. 90
    An Embedded-Processor-Driven Platform for SOC Testing
    by Yu-Ting Hung, 洪郁庭
    Published 2002
    Other Authors: “...Kuen-Jong Lee...”
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  11. 91
    Universal BIST for Heterogeneous Embedded Synchronous Memory cores in SOC
    by Nan-Hsin Tseng, 曾南欣
    Published 2002
    Other Authors: “...Kuen-Jong Lee...”
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  12. 92
    A Sigma-Delta Modulation Based BIST for A/D Converter
    by Ruei-Shiuan Tzeng, 曾瑞鉉
    Published 2002
    Other Authors: “...Kuen-Jong Lee...”
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  13. 93
    3D-IC Built-In Diagnosis Architecture for TSVs with Different Placement and Impact Ranges of Crosstalk Faults
    by Wen-HsuanHsu, 許文軒
    Published 2016
    Other Authors: “...Kuen-Jong Lee...”
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  14. 94
    A Low Cost Memory Built-in Self-Test Architecture and its Design Automation
    by Sheng-Chih Shen, 沈聖智
    Published 2005
    Other Authors: “...Kuen-Jong Lee...”
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  15. 95
    Novel Scan Techniques for Low Power and Low Cost Testing
    by Chia-Ming Ho, 何嘉銘
    Published 2005
    Other Authors: “...Kuen-Jong Lee...”
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  16. 96
    Performance Analysis and Enhancement of SOC Test Platforms
    by Ming-Long Wu, 吳明隆
    Published 2005
    Other Authors: “...Kuen-Jong Lee...”
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  17. 97
    A Reconfigurable Broadcast Scan Architecture for SOC Test Platforms
    by Rei-Lung Chen, 陳瑞嶸
    Published 2005
    Other Authors: “...Kuen-Jong Lee...”
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  18. 98
    Output Compaction Techniques forMultiple Scan Chain Designs
    by Chia-Yang Chen, 陳家揚
    Published 2005
    Other Authors: “...Kuen-Jong Lee...”
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  19. 99
    Output Reduction and Data Compression for System-on-a-Chip
    by Chein-Wei Fang, 方建偉
    Published 2004
    Other Authors: “...Kuen-Jong Lee...”
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  20. 100
    On-Chip Autonomous Test Platform Design for Mobile Electronics and Software Tools for FPGA-based Debugger
    by Kuo-KaiLiu, 留國凱
    Published 2015
    Other Authors: “...Kuen-Jong Lee...”
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