Showing 21 - 27 results of 27 for search 'Shu-Min Li', query time: 0.16s Refine Results
  1. 21
    Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits
    by Yi-Xue Zheng, 鄭意學
    Published 2011
    Other Authors: “...Shu-Min Li...”
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  2. 22
    Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection
    by Kai-Yang Hsieh, 謝鎧仰
    Published 2013
    Other Authors: “...Shu-Min Li...”
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  3. 23
    A Fault Tolerant Routing/Communication Methodology for Reliability Enhancement in Smart Grids
    by Bo-Chuan Cheng, 程柏銓
    Published 2012
    Other Authors: “...Shu-Min Li...”
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  4. 24
    An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package
    by Cheng-you Ho, 何承祐
    Published 2014
    Other Authors: “...Shu-Min Li...”
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  5. 25
    Layout-Aware Multiple Scan Tree Synthesis for 3D IC
    by Yi-Yu Liao, 廖翊宇
    Published 2010
    Other Authors: “...Katherine Shu-Min Li...”
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  6. 26
    Tier-Based Multilevel Interconnect Diagnosis for Through-Silicon-Via
    by Chih-Yun Pai, 白植允
    Published 2010
    Other Authors: “...Katherine Shu-Min Li...”
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  7. 27
    CoNoC: Fast Full Chip Topology Generation for Application-Specific Network on Chip
    by Shu-yu Chen, 陳姝妤
    Published 2010
    Other Authors: “...Katherine Shu-min Li...”
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