Showing 21 - 40 results of 52 for search 'Sying-Jyan Wang', query time: 0.07s Refine Results
  1. 21
    A Study of Low Cost TSV Testing Methods in 3D-IC
    by Yu-Siao Chen, 陳俞孝
    Published 2012
    Other Authors: “...Sying-Jyan Wang...”
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  2. 22
    Optimized Clock Distribution Network Designs with Pre-bond Testability for 3D Stack ICs
    by Cheng-Hao Lin, 林正浩
    Published 2012
    Other Authors: “...Sying-Jyan Wang...”
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  3. 23
    An Integrated High Level Synthesis Method: Scheduling and Resource Allocation for Low Power
    by Chih-Lin Chou, 周志霖
    Published 2003
    Other Authors: “...Sying-Jyan Wang...”
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  4. 24
    power macromodeling based on Analytical Model
    by 劉章瑞
    Published 2003
    Other Authors: “...Sying-Jyan Wang...”
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  5. 25
    A Heuristic Algorithm for Deterministic Test Pattern Based on Continuous Scan
    by Ching-Hung Lin, 林璟鴻
    Published 2003
    Other Authors: “...Sying-Jyan wang...”
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  6. 26
    Reducing Test Pattern in High-Level Testing
    by Teng-Nan Liao, 廖登楠
    Published 2003
    Other Authors: “...Sying-Jyan Wang...”
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  7. 27
    A Technique for Test Compression and Scan Chain Diagnosis Improvement
    by Chien-Liang Chen, 陳建良
    Published 2010
    Other Authors: “...Sying-Jyan Wang...”
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  8. 28
    Analysis of Controlling Circuit Aging with Input Vector Control
    by Jung-Sung Ho, 何融松
    Published 2010
    Other Authors: “...Sying-Jyan Wang...”
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  9. 29
    Test Interface and Integration for High Yield 3D IC Design
    by Ming-Hsien Wu, 鄔明憲
    Published 2010
    Other Authors: “...Sying-Jyan Wang...”
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  10. 30
    Test Data Compression with LFSR-Reseeding and Seed Overlapping
    by Yu-Hsuan Fu, 傅煜烜
    Published 2004
    Other Authors: “...Sying-Jyan Wang...”
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  11. 31
    Simultaneously Reduce Average Power and Peak Power During Behavioral Synthesis：Using Efficient Shared Operation
    by Tung-Hua Yeh, 葉東樺
    Published 2004
    Other Authors: “...Sying-Jyan Wang...”
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  12. 32
    High Level Synthesis for Low Power and Testability
    by Chia-Wen Chen, 鄭嘉文
    Published 2004
    Other Authors: “...Sying-Jyan Wang...”
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  13. 33
    Functional Verification Based on Binary Decision Diagram
    by JaneHangJung, 江政翰
    Published 1999
    Other Authors: “...Sying-Jyan Wang...”
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  14. 34
    Built-In-Self-Test for Embedded memories
    by Chen-Jung Wei, 魏震榮
    Published 1999
    Other Authors: “...Sying-Jyan Wang...”
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  15. 35
    BIST-Based Diagnosis of Interconnect Faults in FPGAs
    by Kuo-En Lee, 李國恩
    Published 1999
    Other Authors: “...Sying-Jyan Wang...”
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  16. 36
    Multiple-Branch Testable Design
    by Ruey-Feng Chen, 陳瑞峰
    Published 1999
    Other Authors: “...Sying-Jyan Wang...”
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  17. 37
    Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
    by Xin Long Li, 李信龍
    Published 2006
    Other Authors: “...Sying Jyan Wang...”
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  18. 38
    Design of Multi-Mode Broadcast under Skew Probability Scan Chain Architecture to Improve Test Data Compression Rate
    by Kuo-Yu Wu, 吳國瑜
    Published 2009
    Other Authors: “...Sying-Jyan Wang...”
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  19. 39
    Fast and Accurate Statistical Static Timing Analysis
    Other Authors: “...Sying-Jyan Wang...”
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  20. 40
    Low Cost DFT for Embedded Passive Components in SIP
    Other Authors: “...Sying-Jyan Wang...”
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