Showing 21 - 40 results of 47 for search 'Tai-Cheng Lee', query time: 0.12s Refine Results
  1. 21
    A Time-to-Digital Converter for ADC Jitter Error Cancellation
    by Chin-Yu Lin, 林晉宇
    Published 2009
    Other Authors: “...Tai-Cheng Lee...”
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  2. 22
    A High-Efficiency and Low-Power Analog-to-Digital Converter
    by Yu-Jung Huang, 黃昱融
    Published 2009
    Other Authors: “...Tai-Cheng Lee...”
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  3. 23
    A 6-bit Gamma-Corrected DAC with a Low-Power Buffer for Column Drivers
    by Cheng-Hsiao Lin, 林政校
    Published 2009
    Other Authors: “...Tai-Cheng Lee...”
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  4. 24
    A 10-bit 50-MS/s Pipelined A/D Converter with Split Background Digital Calibration and Opamp-Sharing Technique
    by Li-Han Hung, 洪立翰
    Published 2009
    Other Authors: “...Tai-Cheng Lee...”
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  5. 25
    The Design and Application of a High-performance DLL
    by Keng-Jan Hsiao, 蕭耕然
    Published 2008
    Other Authors: “...Tai-Cheng Lee...”
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  6. 26
    A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-loop Residue Amplification
    by Fen-Chiu Hsieh, 謝汾秋
    Published 2008
    Other Authors: “...Tai-Cheng Lee...”
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  7. 27
    A Multiphase Clock generator with Self-Calibration Circuits
    by Shih-Chun Lin, 林士鈞
    Published 2008
    Other Authors: “...Tai-Cheng Lee...”
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  8. 28
    Design and Implementation of a 3.125-Gb/s Analog Equalizer for 10GBASE-LX4 Fiber-Optic Communication System
    by Ping Chen, 陳平
    Published 2004
    Other Authors: “...Tai-Cheng Lee...”
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  9. 29
    An Agile 5.2-GHz RF CMOS Frequency Synthesizer
    by Chia-Hsiang Lu, 呂嘉祥
    Published 2004
    Other Authors: “...Tai-Cheng Lee...”
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  10. 30
    Continuous-Time Incremental Delta Sigma Data Converter
    by Ting-Yang Wang, 王鼎洋
    Published 2014
    Other Authors: “...Tai-Cheng Lee...”
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  11. 31
    A Phase Noise Suppression Technique for PLLs with Ring Oscillators
    by Yi-Han Cheng, 鄭伊涵
    Published 2014
    Other Authors: “...Tai-Cheng Lee...”
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  12. 32
    An All Digital PLL for Spread Spectrum Clock Generator
    by Cheng-Dow Su, 蘇承道
    Published 2011
    Other Authors: “...Tai-Cheng Lee...”
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  13. 33
    The Design and Analysis of a Low-Noise Divider-less Fractional-N Synthesizer with Sub-Sampling Phase-Locked Loop Architecture
    by Po-Chun Huang, 黃柏鈞
    Published 2014
    Other Authors: “...Tai-Cheng Lee...”
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  14. 34
    A 10-bit Successive-Approximation A/D Converter with Dynamic Element Matching Technique
    by Po-Huang Huang, 黃博煌
    Published 2014
    Other Authors: “...Tai-Cheng Lee...”
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  15. 35
    A 10Gb/s Equalizer with a Digital Adaptive Algorithm
    by Jui-Cheng Hsiao, 蕭瑞成
    Published 2014
    Other Authors: “...Tai-Cheng Lee...”
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  16. 36
    A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter with Opamp-Sharing Technique
    by Chia-Chi Ho, 何家齊
    Published 2011
    Other Authors: “...Tai-Cheng Lee...”
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  17. 37
    A 2.4GHz High Efficiency Adaptive Power Harvester and Its Management Circuit
    by Cheng-Jyun Li, 李承駿
    Published 2011
    Other Authors: “...Tai-Cheng Lee...”
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  18. 38
    The Design and Analysis of Frequency Synthesizers with Large Multiplication Factors
    by Chieh-Wen Lee, 李介文
    Published 2012
    Other Authors: “...Tai-Cheng Lee...”
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  19. 39
    The Design and Analysis of a Shifted-Averaging VCO-Based Delta-Sigma Modulator
    by Yu-Hsuan Kang, 康毓軒
    Published 2013
    Other Authors: “...Tai-Cheng Lee...”
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  20. 40
    A Wide Range Delay Locked-Loop with Built-in Duty Cycle Correction Circuit
    by Feng-Chia Chang, 張峰嘉
    Published 2008
    Other Authors: “...Tai-Cheng Lee...”
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