Showing 1 - 20 results of 30 for search 'Chang-Jiu Chen', query time: 0.13s Refine Results
  1. 1
    Improving Instruction Dispatch with Dynamic Instruction Reuse
    by Chen, Yi-Ming, 陳奕銘
    Published 1998
    Other Authors: “...Chang-Jiu Chen...”
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  2. 2
    Improving Branch Target Prediction with Register References
    by Liu, Yueh-Hung, 劉岳泓
    Published 1998
    Other Authors: “...Chang-Jiu Chen...”
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  3. 3
    The Study and Improvement of Instruction and Data Prefetching
    by Shieh, Ruey-Pyng, 謝瑞平
    Published 1998
    Other Authors: “...Chang-Jiu Chen...”
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  4. 4
    Improvement for Reducing Latency of Load Instructions
    by Liu, Wen-Jun, 劉文俊
    Published 1998
    Other Authors: “...Chang-Jiu Chen...”
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  5. 5
    Construct QoS end-to-end virtual path using Lagrangean relaxation method
    by Ming-Su Liu, 劉名恕
    Published 2004
    Other Authors: “...Chang-Jiu Chen...”
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  6. 6
    The Study of Multilevel Branch Prediction
    by Gi-Dung Liang, 梁桔端
    Published 2000
    Other Authors: “...Chang-Jiu Chen...”
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  7. 7
    High Bandwidth Instruction Fetch Mechanism
    by Yi-Tao Liao, 廖宜道
    Published 2000
    Other Authors: “...Chang-Jiu Chen...”
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  8. 8
    The Heuristic Trace Selection for Trace Cache
    by Zung-Hang Wu, 吳宗翰
    Published 2000
    Other Authors: “...Chang-Jiu Chen...”
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  9. 9
    Branch Direction Prediction with Vote Predictor
    by Hung-Ching Lin, 林宏慶
    Published 2000
    Other Authors: “...Chang-Jiu Chen...”
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  10. 10
    Self-Timed Torus Interconnection Network with one-of-five encoding
    by Man-Chen Huang, 黃曼珍
    Published 2008
    Other Authors: “...Chang-Jiu Chen...”
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  11. 11
    A Low Power 1-n-1 Structure FIFO implementation with GasP
    by Ming-Tse Sune, 孫銘澤
    Published 2008
    Other Authors: “...Chang-Jiu Chen...”
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  12. 12
    A Flexible Dual-rail 32-bit ALU Design
    by 方秋鈞
    Published 2008
    Other Authors: “...Chang-Jiu Chen...”
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  13. 13
    Design and Evaluation of A X86 CISC/RISC Translation Architecture
    by Lin, Gin Hong, 林經鴻
    Published 1997
    Other Authors: “...Chang-Jiu Chen...”
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  14. 14
    Issues of the RISC Execution Core for a Superscalar CISC Microprocessor
    by Sheu, Yuh-Ren, 許裕仁
    Published 1997
    Other Authors: “...Chang-Jiu Chen...”
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  15. 15
    FR-vector: A new Model for Switching Activity Analysis
    by Zheng-Lung Lin, 林正倫
    Published 2003
    Other Authors: “...Chang-Jiu Chen...”
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  16. 16
    SoC Software/Hardwaer Co-Verification System
    by Wen-Chieh Huang, 黃文傑
    Published 2003
    Other Authors: “...Chang-Jiu Chen...”
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  17. 17
    The Design and Implementation of Asynchronous Processor Simulator
    by Tse-hao Lee, 李則皞
    Published 2001
    Other Authors: “...Chang-Jiu Chen...”
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  18. 18
    A Method of Improving Translating Performance in the CISC/RISC Hybrids
    by Jian, Wen-Bin, 簡文斌
    Published 1996
    Other Authors: “...Chang-Jiu Chen...”
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  19. 19
    Using Pipeline Method to Improve Asynchronous 8051 Processor Performance
    by Ruei-Fu Tsai, 蔡瑞夫
    Published 2006
    Other Authors: “...Chang-Jiu Chen...”
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  20. 20
    Decoder Design of the Asynchronous 8051 Microcontroller
    by Tuan-Chieh Wang, 王端傑
    Published 2006
    Other Authors: “...Chang-Jiu Chen...”
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