Showing 1 - 20 results of 24 for search 'Chao, Chia-Tso', query time: 0.21s Refine Results
  1. 1
    Test Methodology of Defect-based Bridge Fault
    by Hu, Yu-Pang, 胡鈺邦
    Published 2019
    Other Authors: “...Chao, Chia-Tso...”
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  2. 2
    Layout-Based Test Methodology for Intra-Cell Short Defects
    by Li, Dong-Zhen, 李東振
    Published 2019
    Other Authors: “...Chao, Chia-Tso...”
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  3. 3
    DVFS Binning Using Machine-Learning Techniques
    by Chang, Keng-Wei, 張耕瑋
    Published 2017
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  4. 4
    Test methodologies for solving performanceand low-power issues on advanced designs
    by Mu, Szu-Pang, 穆思邦
    Published 2016
    Other Authors: “...Chao, Chia-Tso...”
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  5. 5
    Layout-Based Methodology of Dual-Cell-Aware Tests
    by Wu, Tse-Wei, 吳則緯
    Published 2017
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  6. 6
    Power-Distribution-Network Design Methodologies toward Fast Physical-Design Closure
    by Chang, Wen-Hsiang, 張玟翔
    Published 2018
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  7. 7
    Scan reordering for improving bridge fault coverage based on low-power stuck-at-fault pattern fill
    by Kuo, Chun-Ren, 郭淳仁
    Published 2011
    Other Authors: “...Chao, Chia-Tso...”
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  8. 8
    Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
    by Chen, Kuo-An, 陳擴安
    Published 2011
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  9. 9
    Testing Strategies for Retention Flip-flops
    by Hsu, Hao-Wen, 徐浩文
    Published 2012
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  10. 10
    Comparison and analysis of testing method of open defect for Data-Aware Dynamic-Supply 8T SRAM
    by Huang, Chin-Yuan, 黃欽遠
    Published 2012
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  11. 11
    A Metal-Only ECO Solver for Input-Slew and Output-Loading Violations
    by Chang, Chih-Wei, 張智為
    Published 2010
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  12. 12
    Test methodology and fault modeling for low-power advanced SRAM
    by Lin, Chen-Wei, 林政偉
    Published 2013
    Other Authors: “...Chao, Chia-Tso...”
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  13. 13
    Improving FIB Signal Observability by Utilzing Dummy Metal Fills
    by Tu, Wei-Sen, 涂偉勝
    Published 2010
    Other Authors: “...Chao, Chia-Tso...”
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  14. 14
    Testing open defects for subthreshold SRAM designs
    by Chen, Hung-Hsin, 陳弘昕
    Published 2010
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  15. 15
    Testing Methodology for Low-Power Dual-Port Utilizing Write-Assist Cells Against Simultaneous Access Disturbance
    by Huang, Chao-Ying, 黃召穎
    Published 2013
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  16. 16
    Repair Friendly Layout Generation for FIB Technology
    by Chen, Yu-An, 陳昱安
    Published 2013
    Other Authors: “...Chao, Chia-Tso...”
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  17. 17
    Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
    by Shen, Heng-Cheng, 沈桓丞
    Published 2014
    Other Authors: “...Chao, Chia-Tso...”
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  18. 18
    Methodology of Generating Cell-Aware and Dual-Cell-Aware Tests
    by Huang, Yu-Hao, 黃宇豪
    Published 2016
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  19. 19
    Predicting Vt Variation and Static IR Drop of Ring Oscillators Using Model-Fitting Techniques
    by Huang, Tzu-Hsuan, 黃子軒
    Published 2016
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  20. 20
    Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
    by Lee, Kao-Chi, 李高騏
    Published 2015
    Other Authors: “...Chao, Chia-Tso...”
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