Showing 1 - 20 results of 42 for search 'Huang, Chih-Tsun', query time: 0.20s Refine Results
  1. 1
    VLSI Design of A New High Speed Pipelined Reed-Solomon CODEC
    by Huang Chih-Tsun, 黃稚存
    Published 1996
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  2. 2
    Assisted Design Optimization using High-Level Synthesis Flow
    by Wei-Chun Chang, 張瑋君
    Published 2016
    Other Authors: “...Huang, Chih Tsun...”
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  3. 3
    Design Exploration Methodology for Deep Convolutional Neural Network Accelerator
    by Chen, Chun-Chen, 陳俊辰
    Published 2018
    Other Authors: “...Huang, Chih-Tsun...”
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  4. 4
    Soft Error Analysis for CNN Inference Accelerator with Efficient Dynamic Fixed Point Quantization
    by Wu, Yueh-Chi, 吳岳騏
    Published 2018
    Other Authors: “...Huang, Chih-Tsun...”
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  5. 5
    High Execution Efficiency Accelerator for Stencil Computation
    by Ito, Takahiro, 伊藤剛浩
    Published 2018
    Other Authors: “...Huang, Chih-Tsun...”
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  6. 6
    Fault-Tolerant NoC Design and Analysis for Many-Core Platform
    by Chen, Wei-Ting, 陳韋廷
    Published 2013
    Other Authors: “...Huang, Chih-Tsun...”
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  7. 7
    Optimization of Data Locality for Energy-Efficient Pointwise Convolutional Layers in CNN Inference Accelerators
    by Wu, Hao-Ning, 吳浩寧
    Published 2018
    Other Authors: “...Huang, Chih-Tsun...”
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  8. 8
    Design of an Inference Accelerator for CNN with Sparse Row-wise Kernel
    by Chang, Chia-Hung, 張嘉宏
    Published 2019
    Other Authors: “...Huang, Chih-Tsun...”
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  9. 9
    A Fast Simulation Model of DRAM Controller Based on Transaction Speculation
    by Hsu, Che-Wei, 許哲維
    Published 2017
    Other Authors: “...Huang, Chih-Tsun...”
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  10. 10
    Accelerating Convolutional Neural Networks using Iterative Two-Pass Decomposition
    by Lin, Wei-Shiang, 林暐翔
    Published 2017
    Other Authors: “...Huang, Chih-Tsun...”
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  11. 11
    Design of an Inference Accelerator for Compressed Convolution Neural Networks
    by Ho, Pin-Hui, 何品蕙
    Published 2017
    Other Authors: “...Huang, Chih-Tsun...”
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  12. 12
    Memory Partitioning and Optimization of On-Chip Accelerators with High-Level Synthesis
    by Peng, Te-Hsin., 彭德欣
    Published 2017
    Other Authors: “...Huang, Chih-Tsun...”
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  13. 13
    Cycle-Accurate Model for Application-Specific Packet-Based On-Chip Interconnects and Their Optimization
    by Shih, Yu Ju, 施佑儒
    Published 2016
    Other Authors: “...Huang, Chih-Tsun...”
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  14. 14
    Design of A Flexible Accelerator for Deep Convolution Neural Networks
    by Cai, Pei Yun, 蔡佩妘
    Published 2017
    Other Authors: “...Huang, Chih Tsun...”
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  15. 15
    Modeling and Prototyping the Wireless Test System
    by Chang,Tien-Yu, 張天與
    Published 2008
    Other Authors: “...Huang,Chih-Tsun...”
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  16. 16
    Design and Evaluation of a Power-Adaptive Methodology
    by Chuang,Hsiao-An, 莊孝安
    Published 2008
    Other Authors: “...Huang,Chih-Tsun...”
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  17. 17
    Design of the Low-Density Parity-Check CODEC for Non-Volatile Memories
    by Ho,Chi-Da, 何啟達
    Published 2008
    Other Authors: “...Huang,Chih-Tsun...”
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  18. 18
    Debug and Trace Technology for the Embedded DSP Core
    by Ho, Yen-Ju, 何彥儒
    Published 2008
    Other Authors: “...Huang, Chih-Tsun...”
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  19. 19
    基於晶片網路的多核心平台之暫存器轉換層級實作
    by Chen, Po-Yu, 陳柏宇
    Published 2011
    Other Authors: “...Huang, Chih-Tsun...”
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  20. 20
    Energy Efficient Architecture for Elliptic Curve Cryptography over Binary Fields
    by Chang, Yueh, 張悅
    Published 2011
    Other Authors: “...Huang, Chih-Tsun...”
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