Showing 1 - 20 results of 41 for search 'I. C. Wey', query time: 0.19s Refine Results
  1. 1
    High Frequency Green-Light Photoplethysmography Design for Wearable Applications
    by Yu Liang Liu, 劉昱良
    Published 2019
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  2. 2
    Inherent Setup Time/Hold Time Redundant Soft Error Tolerant Register Design
    by Yen Ting Hou, 侯彥廷
    Published 2019
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  3. 3
    Enhancing Soft Error Tolerance in Dynamic CMOS Circuits by Using C-Element and Source Voltage Boosting
    by Chun Han Chen, 陳俊翰
    Published 2019
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  4. 4
    Soft Error Correction Circuit Design in Cluster Low Voltage System
    by Sheng Yu, 余昇
    Published 2019
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  5. 5
    Wide Range Impedance Measurement Circuit Design for Parkinson\'s Disease
    by Hung Hsiang HU, 胡鴻翔
    Published 2019
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  6. 6
    Low Power Hardware Efficient Wearable Daily Activity Metabolic Equivalent Sensing Chip Design
    by Zhan You Wu, 吳展侑
    Published 2018
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  7. 7
    Non-Cross-Coupled Edge-Triggered Level-Converting Flip-Flop Design For Multi-Supply System
    by Heng Rui Zhou, 周恆睿
    Published 2018
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  8. 8
    Estimating Energy Expenditure in Daily Activities with an Accelerometer
    by Pei Min Huang, 黃珮民
    Published 2017
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  9. 9
    Non-Cross-Coupled Level Shifter
    by Yi Long Chen, 陳逸隆
    Published 2017
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  10. 10
    Design of a Gallium Nitride Transistor based Half-bridge DC-DC Converter
    by Chun Yuan Chen, 陳俊蒝
    Published 2017
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  11. 11
    Using Dual PPG Signal to Realize Continuously Wearable Blood Pressure Monitoring
    by Min Lin Lin, 林明霖
    Published 2017
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  12. 12
    Low-Hardware Cost Soft-Error-Tolerant Arithmetic Circuit Design by Using Hardware-Sharing
    by Chia Liang Sui, 隋佳良
    Published 2012
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  13. 13
    Design and Analysis of near threshold voltage CMOS circuits with low delay variance
    by Yung Sheng Chen, 陳永勝
    Published 2014
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  14. 14
    High Search Efficiency And Low Hardware Cost Dual-Mode Image Motion Estimation Circuit Design
    by Bing Jhe Chi, 蔡秉哲
    Published 2013
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  15. 15
    Low-Voltage Low-Power Image Motion Estimation Circuit Design
    by Sheng Hung Yu, 游勝鴻
    Published 2013
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  16. 16
    Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider
    by Cheng Chang Chen, 陳政昌
    Published 2011
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  17. 17
    Hardware-Efficient, High-Soft-Error-Tolerant Arithmetic Circuit Design based on Most-Significant-Part Main-Block Redundancy
    by Pei Chuen Lan, 藍珮純
    Published 2011
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  18. 18
    Low-Power Algorithmic Noise-Tolerant Circuit Design Based on Gated Main Arithmetic Block and Precise Fixed-Width Reduced Precision Redundancy
    by Yi Ting Chen, 陳羿廷
    Published 2011
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  19. 19
    All Digital Folded Low Hardware Cost Maximum Power Point Tracking Chip Design and Implementation for Photovoltaic /Wind Hybrid Energy System
    by Yung Shun Yang, 楊詠順
    Published 2011
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  20. 20
    Soft error tolerant latch design
    by Ming Yu Lliu, 劉明諭
    Published 2011
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