A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device

by Bing Wang, Zhigang Wang, James B. Kuo
Published 2018-01-01

A Unified Continuous and Discrete Model for Double-Gate MOSFETs With Spatially Varying or Pulsed Doping Profiles

by Chuyang Hong, Jun Zhou, Qi Cheng, Kunkun Zhu, James B. Kuo, Yijian Chen
Published 2017-01-01

A Cache Memory Using SOI DTMOS Technique and a Content-Addressable-Memory Cell Approach

by Yee-Sin Er, 余宇昕
Published 2007

True Single-phase Adiabatic Circuit Techniques

by CHEN HSIN-HUNG, 陳信宏
Published 2002

Direct Bootstrapped Circuit Techniques Suitable for Low-Voltage CMOS VLSI

by pcchen, 陳柏俊
Published 2002

Low Voltage BiCMOS Logic Circuit Design Using Two-Capacitor Bootstrapped Technique

by Hou-Kuan Sung, 宋厚寬
Published 2002

The Adiabatic Logic Circuit Technology Suitable for Low Voltage CMOS VLSI

by HOU-FU CHEN, 陳厚甫
Published 2004

A 2D Analysis for Capacitance Characteristics of Partially-Depleted SOI NMOS Devices

by Wang Shan Jie, 王善杰
Published 2004

Low-Voltage Low-Power CMOS Multiplier Design Using Pipeline Latch High-Level Synthesis Approach

by Wei-Hong Wu, 吳威宏
Published 2010

Modeling the CBE/CBC Capacitance of the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device

by Yu-Heng Cheng, 鄭宇亨
Published 2011

Analysis of the Capacitance Behavior of Narrow-Channel FD SOI NMOS Device Considering the 3D Fringing Capacitances Using 3-D Simulation

by Jian-Zhong Chen, 陳建中
Published 2006

A Compact Threshold Voltage Model for Gate Misalignment Effect of Double-Gate (DG) Fully-Depleted (FD) SOI NMOS Devices

by Chih-Kuo Sun, 孫治國
Published 2003

2-D Simulation Analysis for Gate Misalignment Effects of Double-Gate (DG) SOI MOS Devices

by LIN MING TSE, 林銘澤
Published 2003

Circuit Techniques Suitable for Low-Voltage CMOS VLSI

by Stanley Bo-Ting Wang, 汪柏廷
Published 2000

Low-Voltage Circuit Design Using PD SOI Dynamic-Threshold Voltage MOS (DTMOS) Techniques

by Sheng-Che Liu, 劉聖哲
Published 2000

Modeling of Silicon-on-Insulator (SOI) CMOS VLSI Devices

by Su Ke-Wei, 蘇哿暐
Published 1998

Static and Dynamic Logic Circuit Techniques Suitable for Low-Voltage CMOS VLSI

by Chih-Hong Lou, 樓志宏
Published 1999

Modeling of PD-SOI Dynamic Threshold Voltage MOS (DTMOS) Devices

by Kuo-Hua Yuan, 袁國華
Published 1999

A New Adder and Multiplier Architecture for Low-Voltage VLSI Systems

by Yen-Mou Huang, 黃彥謀
Published 1999

DC and AC Analysis of Tri-Gate Fin-FET Device

by Bo-Han Hsieh, 謝泊含
Published 2006