Showing 1 - 19 results of 19 for search 'Jiang, Hui-Ru', query time: 0.15s Refine Results
  1. 1
    酸雨污染法律問題之研究
    by JIANG,HUI-RU, 姜惠如
    Published 1990
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  2. 2
    iTimer: A Novel and General Timing Analysis Engine for Modern IC Designs
    by Lee, Pei-Yu, 李培瑜
    Published 2018
    Other Authors: “...Jiang, Hui-Ru...”
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  3. 3
    iClaire: A Fast and General Layout Pattern Classification Algorithm
    by Chang, Wei-Chun, 張維均
    Published 2018
    Other Authors: “...Jiang, Hui-Ru...”
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  4. 4
    Toward a Reliable Power Ground Network
    by Zeng, Yu-Kai, 曾郁凱
    Published 2018
    Other Authors: “...Jiang, Hui-Ru...”
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  5. 5
    Dummy Via Insertion for Enhancing Guiding Template Assignment and Layout Decomposition in DSA-MP
    by Yang, Xiang-Jing, 楊翔淨
    Published 2018
    Other Authors: “...Jiang, Hui-Ru...”
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  6. 6
    A Novel Register Clustering Algorithm
    by Chang, Ya-Chu, 張雅筑
    Published 2018
    Other Authors: “...Jiang, Hui-Ru...”
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  7. 7
    Concurrent Timing-Driven Layer Assignment for Multiple Nets at Advanced Technology Nodes
    by Yang, Ting-You, 楊停佑
    Published 2017
    Other Authors: “...Jiang, Hui-Ru...”
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  8. 8
    Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation
    by Chiu, Wei-Lun, 邱緯綸
    Published 2017
    Other Authors: “...Jiang, Hui-Ru...”
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  9. 9
    Unification of rectilinear steiner tree construction for SoC and nanometer technologies
    by Yu, Yen-Ting, 余彥廷
    Published 2009
    Other Authors: “...Jiang, Hui-Ru...”
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  10. 10
    Matching-Based Minimum-Cost Spare Cell Selection for Design Changes
    by Chang, Liang-Gi, 張良吉
    Published 2009
    Other Authors: “...Jiang, Hui-Ru...”
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  11. 11
    Accurate Process-Hotspot Dectection using Critical Design Rule Extraction
    by Chan, Ya-Chung, 詹雅仲
    Published 2011
    Other Authors: “...Jiang, Hui-Ru...”
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  12. 12
    Novel Low Power Sequential Element Replacement: From Multi-Bit Flip-Flops to Pulsed-Latches
    by Chang, Chih-Long, 張之龍
    Published 2013
    Other Authors: “...Jiang, Hui-Ru...”
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  13. 13
    A Circuit-Topology-Guided Discrete Gate Sizing Framework Considering Leakage Power Reduction
    by Tan, Chuan-Yao, 譚傳耀
    Published 2012
    Other Authors: “...Jiang, Hui-Ru...”
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  14. 14
    Clock Power Saving at Placement Using Multi-Bit Flip-Flops
    by Tsai, Chang-Cheng, 蔡昌澄
    Published 2012
    Other Authors: “...Jiang, Hui-Ru...”
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  15. 15
    A TSV Delay Meter for 3D ICs
    by Ho, Cheng-Yeh, 何承曄
    Published 2010
    Other Authors: “...Jiang, Hui-Ru...”
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  16. 16
    Cost Evaluation and Circuit Partitioning for 3D IC
    by Chan, Cheng-Chi, 詹証琪
    Published 2010
    Other Authors: “...Jiang, Hui-Ru...”
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  17. 17
    A novel lithographic hotspot detection framework
    by Yu, Yen-Ting, 余彥廷
    Published 2015
    Other Authors: “...Jiang, Hui-Ru...”
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  18. 18
    Fast Incremental Timing and Incremental CPPR Analysis
    by Li, Cheng-Ruei, 李承睿
    Published 2015
    Other Authors: “...Jiang, Hui-Ru...”
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  19. 19
    Fast Time-to-Market Using Effective Stimulus Generation and Logic Rectification
    by Cheng, An-Che, 鄭安哲
    Published 2015
    Other Authors: “...Jiang, Hui-Ru...”
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