Showing 1 - 20 results of 105 for search 'Kuen-Jong Lee', query time: 0.09s Refine Results
  1. 1
    A Low Power Synthesis Flow for Multi-rate Systems
    by Hsin-PangKuo, 郭興邦
    Published 2016
    Other Authors: “...Kuen-Jong Lee...”
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  2. 2
    Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis
    by Sheng-LinLin, 林盛霖
    Published 2016
    Other Authors: “...Kuen-Jong Lee...”
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  3. 3
    Autonomous Testing for 3D-ICs with IEEE Std. 1687
    by Jin-CunYe, 葉金村
    Published 2016
    Other Authors: “...Kuen-Jong Lee...”
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  4. 4
    High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
    by Bo-RenChen, 陳柏任
    Published 2018
    Other Authors: “...Kuen-Jong Lee...”
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  5. 5
    Test Compression with Single-Input Data Spreader and Multiple Test Sessions
    by Chang-WenChen, 陳昶聞
    Published 2018
    Other Authors: “...Kuen-Jong Lee...”
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  6. 6
    A High-Efficiency Hybrid Multicast Routing Approach for Mesh-Based Networks-on-Chip
    by Chun-WeiWu, 吳俊緯
    Published 2018
    Other Authors: “...Kuen-Jong Lee...”
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  7. 7
    Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run
    by Yi-ChengKung, 龔宜成
    Published 2019
    Other Authors: “...Kuen-Jong Lee...”
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  8. 8
    A Novel Test Generation Method for Small-Delay Defects with User-defined Fault Model
    by Chao-JunShang, 商朝鈞
    Published 2019
    Other Authors: “...Kuen-Jong Lee...”
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  9. 9
    Time-Related Hardware Trojan Attacks on Processor Cores
    by Man-HsuanKuo, 郭蔓萱
    Published 2019
    Other Authors: “...Kuen-Jong Lee...”
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  10. 10
    An Efficient Diagnosis Method to Deal with Multiple Fault-Pairs Simultaneously Using a Single Circuit Model
    by Cheng-HungWu, 吳政鴻
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  11. 11
    A Throughput Driven High Level Synthesis Algorithm to Synthesize Circuits with Multiple Sampling Rates
    by Chung-ChiaHsu, 許峻嘉
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  12. 12
    On-Chip 3D-IC Test System Design for Pre-bond, Post-bond, TSV Test and TSV Diagnosis Based on IEEE 1838 Standard
    by Liang-CheLi, 李良哲
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  13. 13
    Efficient Pattern Generation and Observation Point Insertion for Transition Fault Diagnosis
    by Yi-DaWang, 王奕達
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  14. 14
    A Low Area Overhead BIST Architecture Based on Response Feedback and Logic Reseeding
    by Chung-MinShiao, 蕭崇閔
    Published 2014
    Other Authors: “...Kuen-Jong Lee...”
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  15. 15
    A Run-Pause-Resume Silicon Debug Technique with Cycle-Granularity for Multiple Clock Domain Systems
    by Shuo-LianHong, 洪碩聯
    Published 2017
    Other Authors: “...Kuen-Jong Lee...”
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  16. 16
    Test and Diagnosis Methodology for Various Fault Models in Logic Circuits
    by Cheng-HungWu, 吳政鴻
    Published 2018
    Other Authors: “...Kuen-Jong Lee...”
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  17. 17
    Built-In Self Test Circuit Design for SDRAM
    by Hu Wen Xuan, 胡文軒
    Published 2000
    Other Authors: “...Kuen-Jong Lee...”
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  18. 18
    A HIERARCHICAL TEST CONTROL ARCHITECTURE FOR SYSTEM-ON-A-CHIP DESIGN
    by Cheng-I Huang, 黃正儀
    Published 2000
    Other Authors: “...Kuen-Jong Lee...”
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  19. 19
    Teslog: An Interactive Schematic Generation System for Logic Design and Testing
    Other Authors: “...Kuen-Jong Lee...”
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  20. 20
    Test Vector Compaction for Multiple Circuits
    Other Authors: “...Kuen-Jong Lee...”
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