Showing 1 - 20 results of 29 for search 'Mak, Wai-Kei', query time: 0.12s Refine Results
  1. 1
    VLSI Placement for Modern Design with Double-Row Height Standard Cells Considering Power Line Alignment Constraint
    by Lin, Chao Ching, 林晁慶
    Published 2016
    Other Authors: “...Mak, Wai Kei...”
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  2. 2
    Performance Driven Logic Replication for FPGA Emulation System
    by Chen, Chih Heng, 陳致亨
    Published 2016
    Other Authors: “...Mak, Wai Kei...”
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  3. 3
    Considering Via Manufacturability with Directed Self-Assembly at Post-Routing Stage Using Wire Perturbation and Dummy Via Insertion
    by Hsiao, Bo-Yuan., 蕭博元
    Published 2018
    Other Authors: “...Mak, Wai-Kei...”
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  4. 4
    Security-Aware Bipartitioning For 2.5D IC Packaging
    by Hu, Ting-Wei, 胡庭瑋
    Published 2019
    Other Authors: “...Mak, Wai-Kei....”
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  5. 5
    Minimum Implant Area-Aware Placement and Threshold Voltage Refinement
    by Zhang, Shi-Han, 張仕函
    Published 2017
    Other Authors: “...Mak, Wai-Kei...”
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  6. 6
    Mixed-Cell-Height Standard Cell Placement Legalization
    by Hung, Chung-Yao, 洪崇堯
    Published 2017
    Other Authors: “...Mak, Wai-Kei...”
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  7. 7
    Optimizing DSA-MP Decomposition and Redundant Via Insertion with Dummy Vias
    by Chou, Peng-Yi, 周朋毅
    Published 2017
    Other Authors: “...Mak, Wai-Kei...”
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  8. 8
    Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
    by Kuo, Wan-Sin, 郭婉心
    Published 2018
    Other Authors: “...Mak, Wai-Kei...”
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  9. 9
    Single-Cell-Height Detailed Placement Considering Multi-Cell Spacing Constraints
    by Huang, Ding-Wei, 黃鼎崴
    Published 2018
    Other Authors: “...Mak, Wai-Kei...”
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  10. 10
    使用偏斜常態分布的精確封閉形式的參數化塊狀基礎統計時序分析
    Other Authors: “...Mak,Wai-Kei...”
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  11. 11
    ALMmap: Technology mapping for FPGAs with Adaptive Logic Modules
    by Liang, Yu-Yi, 梁有毅
    Published 2011
    Other Authors: “...Mak, Wai-Kei...”
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  12. 12
    針對輸入輸出訊號歪斜的平面規劃漸進式改良方法
    by Luo, Yi-Yang, 羅毅揚
    Published 2011
    Other Authors: “...Mak, Wai-Kei...”
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  13. 13
    A novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules
    by Wu, Sheng-Kai, 吳聖凱
    Published 2013
    Other Authors: “...Mak, Wai-Kei...”
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  14. 14
    An Efficient Approach to Block-based Statistical Timing Analysis
    by Hsu, Po-Yi, 許博一
    Published 2013
    Other Authors: “...Mak, Wai-Kei...”
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  15. 15
    Floorplanning,TSVAssignmentandPinAssignmentfor3D-ICDesigns
    by Feng, Kuan-Chung, 馮冠中
    Published 2010
    Other Authors: “...Mak, Wai-Kei...”
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  16. 16
    固定框架之三維度積體電路樓層規劃同時考慮直通矽穿孔的配置
    by Li, Cha-Ru, 李佳儒
    Published 2010
    Other Authors: “...Mak, Wai Kei...”
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  17. 17
    Wirelength-Driven Incremental TSV Redistribution on 3-D IC Floorplanning
    by Lin, Yung Shun, 林雍舜
    Published 2013
    Other Authors: “...Mak, Wai-Kei...”
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  18. 18
    On Efficient Static Timing Analysis
    by Kuo, Tien-Yu, 郭天鈺
    Published 2012
    Other Authors: “...Mak, Wai-Kei...”
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  19. 19
    Voltage Island-aware Floorplanning for SoC design
    by Tang, Chih-Chieh, 唐志傑
    Published 2009
    Other Authors: “...Mak, Wai-Kei...”
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  20. 20
    線性規劃之三維晶片整合分割
    Other Authors: “...Mak, Wai-Kei...”
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