Showing 1 - 20 results of 96 for search 'SHEN-IUAN LIU', query time: 0.21s Refine Results
  1. 1
    Low TC Relaxation Oscillators with Digital Compensation
    by Yi-An Chang, 張亦安
    Published 2017
    Other Authors: “...Shen-Iuan Liu...”
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  2. 2
    A Low-Power High-Channel-Loss Equalizer with CTLE, 3-Tap DFE and SSLMS in 0.11um CMOS process
    by Yong-Ren Fang, 方詠仁
    Published 2018
    Other Authors: “...Shen-Iuan Liu...”
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  3. 3
    A 1.5-6 Gb/s Clock and Data Recovery Circuit Reducing Cycle Slipping
    by Wei-Liang Lin, 林偉良
    Published 2019
    Other Authors: “...Shen-Iuan Liu...”
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  4. 4
    A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency JTOL
    by Shun-Chi Chang, 張舜棋
    Published 2019
    Other Authors: “...Shen-Iuan Liu...”
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  5. 5
    A Phase-Locked Loop Using a Single-Ring-Oscillator-Based Integrator and a Digital Phase-Locked Loop With Adaptive Loop Gain Controller
    by Guan-Yu Su, 蘇冠宇
    Published 2019
    Other Authors: “...Shen-Iuan Liu...”
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  6. 6
    A Low-Power and Small-Area Jitter Detector Using Asynchronous Sampling
    by Hsien-Che Chen, 陳先哲
    Published 2017
    Other Authors: “...Shen-Iuan Liu...”
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  7. 7
    An 8 Gb/s Adaptive Receiver with Eye-width Detection
    by Sheng-How Tseng, 曾聖豪
    Published 2018
    Other Authors: “...Shen-Iuan Liu...”
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  8. 8
    A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD
    by Yu-Kai CHIU, 邱鈺凱
    Published 2019
    Other Authors: “...Shen-Iuan Liu...”
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  9. 9
    The Equalizers with Adaptive Techniques in High-Speed Backplane Communication
    by Yu-Ming Ying, 顏宇明
    Published 2011
    Other Authors: “...Shen-Iuan Liu...”
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  10. 10
    Design of 20Gbps Adaptive Linear Equalizer and Decision Feedback Equalizer
    by Kuan-Yu Chen, 陳冠宇
    Published 2016
    Other Authors: “...Shen-Iuan Liu...”
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  11. 11
    Realization of a Cyclic ADC with Split Architecture and Digital Background Calibration
    by Ing-June Lu, 盧盈君
    Published 2008
    Other Authors: “...Shen-Iuan Liu...”
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  12. 12
    Design and Implementation of Bang-Bang Phase/Frequency Detectors
    by Shao-Hung Lin, 林紹弘
    Published 2007
    Other Authors: “...Shen-Iuan Liu...”
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  13. 13
    3.125Gbps Ethernet transmitter for IEEE 802.3a.e.
    by Hung-Chun Chen, 陳鴻鈞
    Published 2005
    Other Authors: “...Shen-Iuan Liu...”
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  14. 14
    5.2GHz CMOS RF Image-Rejection Mixers
    by Lan Chi-Han, 藍祺漢
    Published 2002
    Other Authors: “...Shen-Iuan Liu...”
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  15. 15
    Design of A PLL with Fast-Lock and Low Jitter
    by SHAO-KU KAO, 高少谷
    Published 2002
    Other Authors: “...Shen-Iuan Liu...”
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  16. 16
    Digital Error-Averaging Technique for Pipelined Analog to Digital Converter
    by Hweiyu Lee, 黎慧玉
    Published 2002
    Other Authors: “...Shen -Iuan Liu...”
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  17. 17
    A 1.0-V, 10-Bit CMOS Pipelined Analog-to-Digital Converter
    by Kuang-Wei Cheng, 鄭光偉
    Published 2002
    Other Authors: “...Shen-Iuan Liu...”
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  18. 18
    8-bit, High Conversion Rate Pipelined ADC with Improved Capacitors
    by Chih-Min Liu, 劉智民
    Published 2002
    Other Authors: “...Shen-Iuan Liu...”
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  19. 19
    Design and Implementation of Clock Generators with Charge Pump Calibration in CMOS/LTPS Technology
    by Wei-Ming Lin, 林韋名
    Published 2010
    Other Authors: “...Shen-Iuan Liu...”
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  20. 20
    Phase-Locked Loops Using Self-Healing Circuits and Fast-Locking Technique
    by Yun-Ta Tsai, 蔡昀達
    Published 2010
    Other Authors: “...Shen-Iuan Liu...”
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