Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor
Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only c...
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MDPI AG
2020-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/7/1165 |
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doaj-027f2bc6564343c49bb029a93d3a2b0f2020-11-25T03:47:57ZengMDPI AGElectronics2079-92922020-07-0191165116510.3390/electronics9071165Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded ProcessorXiang Wang0Zongmin Zhao1Dongdong Xu2Zhun Zhang3Qiang Hao4Mengchen Liu5Yu Si6School of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaNowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, the integrity check technology based on the basic block (BB) is utilized to monitor the program execution in real-time, while the rollback operation is taken once the integrity check is failed. In addition, a Monitoring Cache (M-Cache) is built to buffer the reference data for integrity checking. Moreover, a recovery strategy mainly for three tampered positions (registers in processor, instructions in Cache, and codes in memory) is provided to ensure the smooth running of the embedded system. Finally, the open RISC processor is adopted to implement and verify the presented security architecture, which has been proved to be effective for program detection in the execution of tamper attack and quick recovery of the running environment as well as code.https://www.mdpi.com/2079-9292/9/7/1165embedded processorprogram execution securityintegrity checkfault recoverycheckpoint backupcheckpoint rolling back |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Xiang Wang Zongmin Zhao Dongdong Xu Zhun Zhang Qiang Hao Mengchen Liu Yu Si |
| spellingShingle |
Xiang Wang Zongmin Zhao Dongdong Xu Zhun Zhang Qiang Hao Mengchen Liu Yu Si Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor Electronics embedded processor program execution security integrity check fault recovery checkpoint backup checkpoint rolling back |
| author_facet |
Xiang Wang Zongmin Zhao Dongdong Xu Zhun Zhang Qiang Hao Mengchen Liu Yu Si |
| author_sort |
Xiang Wang |
| title |
Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor |
| title_short |
Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor |
| title_full |
Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor |
| title_fullStr |
Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor |
| title_full_unstemmed |
Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor |
| title_sort |
two-stage checkpoint based security monitoring and fault recovery architecture for embedded processor |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2020-07-01 |
| description |
Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, the integrity check technology based on the basic block (BB) is utilized to monitor the program execution in real-time, while the rollback operation is taken once the integrity check is failed. In addition, a Monitoring Cache (M-Cache) is built to buffer the reference data for integrity checking. Moreover, a recovery strategy mainly for three tampered positions (registers in processor, instructions in Cache, and codes in memory) is provided to ensure the smooth running of the embedded system. Finally, the open RISC processor is adopted to implement and verify the presented security architecture, which has been proved to be effective for program detection in the execution of tamper attack and quick recovery of the running environment as well as code. |
| topic |
embedded processor program execution security integrity check fault recovery checkpoint backup checkpoint rolling back |
| url |
https://www.mdpi.com/2079-9292/9/7/1165 |
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