An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method
The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unaccepta...
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doaj-09c4cbb1843e45d0bb16fdbd2086de402020-11-25T03:08:39ZengMDPI AGElectronics2079-92922020-03-01958058010.3390/electronics9040580An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning MethodPeng Cao0Wei Bao1Jingjing Guo2National ASIC System Engineering Center, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Center, Southeast University, Nanjing 210096, ChinaNational ASIC System Engineering Center, Southeast University, Nanjing 210096, ChinaThe wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.https://www.mdpi.com/2079-9292/9/4/580PVT cornerspath delay predictionensemble modelCNN feature extractor |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Peng Cao Wei Bao Jingjing Guo |
spellingShingle |
Peng Cao Wei Bao Jingjing Guo An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method Electronics PVT corners path delay prediction ensemble model CNN feature extractor |
author_facet |
Peng Cao Wei Bao Jingjing Guo |
author_sort |
Peng Cao |
title |
An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method |
title_short |
An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method |
title_full |
An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method |
title_fullStr |
An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method |
title_full_unstemmed |
An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method |
title_sort |
accurate and efficient timing prediction framework for wide supply voltage design based on learning method |
publisher |
MDPI AG |
series |
Electronics |
issn |
2079-9292 |
publishDate |
2020-03-01 |
description |
The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods. |
topic |
PVT corners path delay prediction ensemble model CNN feature extractor |
url |
https://www.mdpi.com/2079-9292/9/4/580 |
work_keys_str_mv |
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