Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation

• Main Authors: Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong-Ook Jung
• Format: Article
• Language: English
• Published: IEEE 2021-01-01
• Series: IEEE Access
• Subjects: 7T bitcell; half-select issue; low energy consumption; near-threshold voltage; static random access memory (SRAM)
• Online Access: https://ieeexplore.ieee.org/document/9415630/

Near-threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula>) operation is an effective method for lowering energy consumption. However, it increases the impact of <inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula> variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near-<inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula> region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5&#x0025; and 6&#x0025; higher SRAM operating frequency and 70&#x0025; and 23&#x0025; lower operation energy consumption with a 33&#x0025; and 49&#x0025; smaller bitcell area, respectively.