The Impact of Time Delays for Power Hardware-in-the-Loop Investigations

• Main Authors: Jana Ihrens, Stefan Möws, Lennard Wilkening, Thorsten A. Kern, Christian Becker
• Format: Article
• Language: English
• Published: MDPI AG 2021-05-01
• Series: Energies
• Subjects: power hardware-in-the-loop (PHiL); communication protocols; time delays; modeling and simulation; hardware under test (HUT); rest of system (ROS)
• Online Access: https://www.mdpi.com/1996-1073/14/11/3154

Power hardware-in-the-loop (PHiL) simulations provide a powerful environment in the critical process of testing new components and controllers. In this work, we aim to explain the impact of time delays in a PHiL setup and recommend how to consider them in different investigations. The general concept of PHiL, with its necessary components, is explained and the benefits compared to pure simulation and implemented field tests are presented. An example for a flexible PHiL environment is shown in form of the Power Hardware-in-the-Loop Simulation Laboratory (PHiLsLab) at TU Hamburg. In the PHiLsLab, different hardware components are used as the simulator to provide a grid interface via an amplifier system, a real-time simulator by OPAL-RT, a programmable logic controller by Bachmann, and an M-DUINO microcontroller. Benefits and limitations of the different simulators are shown using case examples of conducted investigations. Essentially, all platforms prove to be appropriate and sufficiently powerful simulators, if the time constants and complexity of the investigated case fit the simulator performance. The communication interfaces used between simulator and amplifier system differ in communication speed and delay; therefore, they have to be considered to determine the level of dynamic interactions between the simulated rest of system and the hardware under test.