Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA
Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the c...
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doaj-0f00c51c4fa94a64bc484107fe898dd02020-11-25T02:53:50ZengMDPI AGSustainability2071-10502020-04-01123068306810.3390/su12083068Enabling Packet Classification with Low Update Latency for SDN Switch on FPGAChenglong Li0Tao Li1Junnan Li2Zilin Shi3Baosheng Wang4Computer College, National University of Defense Technology, Changsha 410073, ChinaComputer College, National University of Defense Technology, Changsha 410073, ChinaComputer College, National University of Defense Technology, Changsha 410073, ChinaComputer College, National University of Defense Technology, Changsha 410073, ChinaComputer College, National University of Defense Technology, Changsha 410073, ChinaField Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.https://www.mdpi.com/2071-1050/12/8/3068SDN switchPacket Classificationupdate latencyBit-VectorFPGA |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Chenglong Li Tao Li Junnan Li Zilin Shi Baosheng Wang |
spellingShingle |
Chenglong Li Tao Li Junnan Li Zilin Shi Baosheng Wang Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA Sustainability SDN switch Packet Classification update latency Bit-Vector FPGA |
author_facet |
Chenglong Li Tao Li Junnan Li Zilin Shi Baosheng Wang |
author_sort |
Chenglong Li |
title |
Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA |
title_short |
Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA |
title_full |
Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA |
title_fullStr |
Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA |
title_full_unstemmed |
Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA |
title_sort |
enabling packet classification with low update latency for sdn switch on fpga |
publisher |
MDPI AG |
series |
Sustainability |
issn |
2071-1050 |
publishDate |
2020-04-01 |
description |
Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively. |
topic |
SDN switch Packet Classification update latency Bit-Vector FPGA |
url |
https://www.mdpi.com/2071-1050/12/8/3068 |
work_keys_str_mv |
AT chenglongli enablingpacketclassificationwithlowupdatelatencyforsdnswitchonfpga AT taoli enablingpacketclassificationwithlowupdatelatencyforsdnswitchonfpga AT junnanli enablingpacketclassificationwithlowupdatelatencyforsdnswitchonfpga AT zilinshi enablingpacketclassificationwithlowupdatelatencyforsdnswitchonfpga AT baoshengwang enablingpacketclassificationwithlowupdatelatencyforsdnswitchonfpga |
_version_ |
1724724178749227008 |