The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

• Main Authors: Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon
• Format: Article
• Language: English
• Published: MDPI AG 2017-02-01
• Series: Sensors
• Subjects: through-silicon via; stereo matching processor; technology scaling; low-power
• Online Access: http://www.mdpi.com/1424-8220/17/2/426

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.