High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

• Main Authors: Haibo Yi, Zhe Nie
• Format: Article
• Language: English
• Published: SpringerOpen 2018-05-01
• Series: EURASIP Journal on Wireless Communications and Networking
• Subjects: Cryptographic system; Multivariate-Quadratic-Equations Public Key Cryptography (MPKC); Multivariate signature; Field-Programmable Gate Array (FPGA)
• Online Access: http://link.springer.com/article/10.1186/s13638-018-1117-2

Abstract Multivariate signature belongs to Multivariate-Quadratic-Equations Public Key Cryptography (MPKC), which is secure to quantum computer attacks. Compared with RSA and ECC, it is required to speed up multivariate signature implementations. A high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this paper. The main computations of signature generations of multivariate schemes are additions, multiplications, inversions, and solving systems of linear equations (LSEs) in a finite field. Thus, we improve the finite field multiplications via using composite field expression and design a finite field inversion via using binary trees. Besides, we improve solving LSEs in a finite field based on a variant algorithm of Gauss-Jordan elimination and use the XOR gates to compute additions. We implement the high-speed hardware architecture based on the above improvements on an Altera Stratix Field-Programmable Gate Array (FPGA), which shows that it takes only 90 clock cycles and 0.9 μs to generate a multivariate signature. The comparison shows that the hardware architecture is much faster than other implementations.