Wu’s Characteristic Set Method for SystemVerilog Assertions Verification
We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2013-01-01
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| Series: | Journal of Applied Mathematics |
| Online Access: | http://dx.doi.org/10.1155/2013/740194 |
| Summary: | We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation. |
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| ISSN: | 1110-757X 1687-0042 |