APA (7th ed.) Citation

Raveendran, S., Edavoor, P. J., Kumar, Y. B. N., & Vasantha, M. H. (2021). Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE.

Chicago Style (17th ed.) Citation

Raveendran, Sithara, Pranose J. Edavoor, Y. B. Nithin Kumar, and M. H. Vasantha. Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE, 2021.

MLA (8th ed.) Citation

Raveendran, Sithara, et al. Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE, 2021.