Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic
This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4:2 compressor optimised for realisation using reversible logic. The proposed inexact 4:2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the...
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doaj-1dd955e1af4148e0b6c87f839ebc094c2021-08-06T23:00:38ZengIEEEIEEE Access2169-35362021-01-01910811910813010.1109/ACCESS.2021.31008929500194Inexact Signed Wallace Tree Multiplier Design Using Reversible LogicSithara Raveendran0https://orcid.org/0000-0001-5805-232XPranose J. Edavoor1https://orcid.org/0000-0002-2133-7126Y. B. Nithin Kumar2https://orcid.org/0000-0001-7446-9424M. H. Vasantha3Department of Electronics and Communication Engineering, National Institute of Technology Goa, Farmagudi, Goa, IndiaDepartment of Electrical and Electronics Engineering, National Institute of Technology Goa, Farmagudi, Goa, IndiaDepartment of Electronics and Communication Engineering, National Institute of Technology Goa, Farmagudi, Goa, IndiaDepartment of Electronics and Communication Engineering, National Institute of Technology Goa, Farmagudi, Goa, IndiaThis paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4:2 compressor optimised for realisation using reversible logic. The proposed inexact 4:2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4:2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4:2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4:2 compressor. An <inline-formula> <tex-math notation="LaTeX">$8\,\, \times \,\,8$ </tex-math></inline-formula> Baugh-Wooley Wallace tree multiplier is implemented in this paper. The accuracy metrics MED and MRED are measured for the proposed multiplier and is found to be the least among existing inexact compressor based multiplier designs. MED and MRED of the proposed multiplier is 59.16 and 0.0109 respectively. The proposed multiplier is utilised in two applications 1) image processing - one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%.https://ieeexplore.ieee.org/document/9500194/Inexact Wallace tree multipliersBaugh-Wooley algorithminexact 4:2 compressorreversible logicimage processingwavelet transform |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Sithara Raveendran Pranose J. Edavoor Y. B. Nithin Kumar M. H. Vasantha |
spellingShingle |
Sithara Raveendran Pranose J. Edavoor Y. B. Nithin Kumar M. H. Vasantha Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic IEEE Access Inexact Wallace tree multipliers Baugh-Wooley algorithm inexact 4:2 compressor reversible logic image processing wavelet transform |
author_facet |
Sithara Raveendran Pranose J. Edavoor Y. B. Nithin Kumar M. H. Vasantha |
author_sort |
Sithara Raveendran |
title |
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic |
title_short |
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic |
title_full |
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic |
title_fullStr |
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic |
title_full_unstemmed |
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic |
title_sort |
inexact signed wallace tree multiplier design using reversible logic |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2021-01-01 |
description |
This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4:2 compressor optimised for realisation using reversible logic. The proposed inexact 4:2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4:2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4:2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4:2 compressor. An <inline-formula> <tex-math notation="LaTeX">$8\,\, \times \,\,8$ </tex-math></inline-formula> Baugh-Wooley Wallace tree multiplier is implemented in this paper. The accuracy metrics MED and MRED are measured for the proposed multiplier and is found to be the least among existing inexact compressor based multiplier designs. MED and MRED of the proposed multiplier is 59.16 and 0.0109 respectively. The proposed multiplier is utilised in two applications 1) image processing - one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%. |
topic |
Inexact Wallace tree multipliers Baugh-Wooley algorithm inexact 4:2 compressor reversible logic image processing wavelet transform |
url |
https://ieeexplore.ieee.org/document/9500194/ |
work_keys_str_mv |
AT sithararaveendran inexactsignedwallacetreemultiplierdesignusingreversiblelogic AT pranosejedavoor inexactsignedwallacetreemultiplierdesignusingreversiblelogic AT ybnithinkumar inexactsignedwallacetreemultiplierdesignusingreversiblelogic AT mhvasantha inexactsignedwallacetreemultiplierdesignusingreversiblelogic |
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