The design of scalar AES Instruction Set Extensions for RISC-V
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic IS...
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Ruhr-Universität Bochum
2020-12-01
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doaj-1ea4cc8289a140acb5ae39ab1b9af4ba2021-02-02T13:45:57ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252020-12-012021110.46586/tches.v2021.i1.109-136The design of scalar AES Instruction Set Extensions for RISC-VBen Marshall0G. Richard Newell1Dan Page2Markku-Juhani O. Saarinen3Claire Wolf4Department of Computer Science, University of BristolMicrochip Technology Inc., USADepartment of Computer Science, University of BristolPQShield, UKSymbiotic EDA Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process. https://tches.iacr.org/index.php/TCHES/article/view/8729ISEAESRISC-V |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Ben Marshall G. Richard Newell Dan Page Markku-Juhani O. Saarinen Claire Wolf |
spellingShingle |
Ben Marshall G. Richard Newell Dan Page Markku-Juhani O. Saarinen Claire Wolf The design of scalar AES Instruction Set Extensions for RISC-V Transactions on Cryptographic Hardware and Embedded Systems ISE AES RISC-V |
author_facet |
Ben Marshall G. Richard Newell Dan Page Markku-Juhani O. Saarinen Claire Wolf |
author_sort |
Ben Marshall |
title |
The design of scalar AES Instruction Set Extensions for RISC-V |
title_short |
The design of scalar AES Instruction Set Extensions for RISC-V |
title_full |
The design of scalar AES Instruction Set Extensions for RISC-V |
title_fullStr |
The design of scalar AES Instruction Set Extensions for RISC-V |
title_full_unstemmed |
The design of scalar AES Instruction Set Extensions for RISC-V |
title_sort |
design of scalar aes instruction set extensions for risc-v |
publisher |
Ruhr-Universität Bochum |
series |
Transactions on Cryptographic Hardware and Embedded Systems |
issn |
2569-2925 |
publishDate |
2020-12-01 |
description |
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.
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topic |
ISE AES RISC-V |
url |
https://tches.iacr.org/index.php/TCHES/article/view/8729 |
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