Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upse...
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doaj-20c47a53a273458ab46b8f6ad6c119372021-09-09T13:42:18ZengMDPI AGElectronics2079-92922021-09-01102148214810.3390/electronics10172148Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography ApplicationLaurent Gantel0Quentin Berthet1Emna Amri2Alexandre Karlov3Andres Upegui4inIT, Hepia, University of Applied Sciences and Arts of Western Switzerland, 1202 Geneva, SwitzerlandinIT, Hepia, University of Applied Sciences and Arts of Western Switzerland, 1202 Geneva, SwitzerlandCYSEC SA EPFL Innovation Park, 1015 Lausanne, SwitzerlandCYSEC SA EPFL Innovation Park, 1015 Lausanne, SwitzerlandinIT, Hepia, University of Applied Sciences and Arts of Western Switzerland, 1202 Geneva, SwitzerlandWith the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.https://www.mdpi.com/2079-9292/10/17/2148FPGAfault-toleranceSEUTMRnano-satellitedynamic and partial reconfiguration |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Laurent Gantel Quentin Berthet Emna Amri Alexandre Karlov Andres Upegui |
spellingShingle |
Laurent Gantel Quentin Berthet Emna Amri Alexandre Karlov Andres Upegui Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application Electronics FPGA fault-tolerance SEU TMR nano-satellite dynamic and partial reconfiguration |
author_facet |
Laurent Gantel Quentin Berthet Emna Amri Alexandre Karlov Andres Upegui |
author_sort |
Laurent Gantel |
title |
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application |
title_short |
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application |
title_full |
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application |
title_fullStr |
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application |
title_full_unstemmed |
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application |
title_sort |
fault-tolerant fpga-based nanosatellite balancing high-performance and safety for cryptography application |
publisher |
MDPI AG |
series |
Electronics |
issn |
2079-9292 |
publishDate |
2021-09-01 |
description |
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability. |
topic |
FPGA fault-tolerance SEU TMR nano-satellite dynamic and partial reconfiguration |
url |
https://www.mdpi.com/2079-9292/10/17/2148 |
work_keys_str_mv |
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