Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code

Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code

In this paper, a three-dimensional polar code (3D-PC) scheme is proposed to improve the error floor performance of parallel concatenated systematic polar code (PCSPC). The proposed 3D-PC is constructed by serially concatenating the PCSPC with a rate-1 third dimension, where only a fraction λ of pari...

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Main Authors: Zhenzhen Liu, Kai Niu, Chao Dong, Jiaru Lin
Format: Article
Language:English
Published: Hindawi-Wiley 2018-01-01
Series:Wireless Communications and Mobile Computing
Online Access:http://dx.doi.org/10.1155/2018/8928761
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spelling doaj-2206cab962324aa093c5e48b5c3469342020-11-25T02:16:48ZengHindawi-WileyWireless Communications and Mobile Computing1530-86691530-86772018-01-01201810.1155/2018/89287618928761Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar CodeZhenzhen Liu0Kai Niu1Chao Dong2Jiaru Lin3Key Laboratory of Universal Wireless Communications, Ministry of Education, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaKey Laboratory of Universal Wireless Communications, Ministry of Education, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaKey Laboratory of Universal Wireless Communications, Ministry of Education, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaKey Laboratory of Universal Wireless Communications, Ministry of Education, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaIn this paper, a three-dimensional polar code (3D-PC) scheme is proposed to improve the error floor performance of parallel concatenated systematic polar code (PCSPC). The proposed 3D-PC is constructed by serially concatenating the PCSPC with a rate-1 third dimension, where only a fraction λ of parity bits of PCSPC are extracted to participate in the subsequent encoding. It takes full advantage of the characteristics of parallel concatenation and serial concatenation. In addition, the convergence behavior of 3D-PC is analyzed by the extrinsic information transfer (EXIT) chart. The convergence loss between PCSPC λ=0 and different λ provides the reference for choosing the value of λ for 3D-PC. Finally, the simulation results confirm that the proposed 3D-PC scheme lowers the error floor.http://dx.doi.org/10.1155/2018/8928761
collection DOAJ
language English
format Article
sources DOAJ
author Zhenzhen Liu
Kai Niu
Chao Dong
Jiaru Lin
spellingShingle Zhenzhen Liu
Kai Niu
Chao Dong
Jiaru Lin
Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
Wireless Communications and Mobile Computing
author_facet Zhenzhen Liu
Kai Niu
Chao Dong
Jiaru Lin
author_sort Zhenzhen Liu
title Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
title_short Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
title_full Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
title_fullStr Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
title_full_unstemmed Adding a Rate-1 Third Dimension to Parallel Concatenated Systematic Polar Code: 3D Polar Code
title_sort adding a rate-1 third dimension to parallel concatenated systematic polar code: 3d polar code
publisher Hindawi-Wiley
series Wireless Communications and Mobile Computing
issn 1530-8669
1530-8677
publishDate 2018-01-01
description In this paper, a three-dimensional polar code (3D-PC) scheme is proposed to improve the error floor performance of parallel concatenated systematic polar code (PCSPC). The proposed 3D-PC is constructed by serially concatenating the PCSPC with a rate-1 third dimension, where only a fraction λ of parity bits of PCSPC are extracted to participate in the subsequent encoding. It takes full advantage of the characteristics of parallel concatenation and serial concatenation. In addition, the convergence behavior of 3D-PC is analyzed by the extrinsic information transfer (EXIT) chart. The convergence loss between PCSPC λ=0 and different λ provides the reference for choosing the value of λ for 3D-PC. Finally, the simulation results confirm that the proposed 3D-PC scheme lowers the error floor.
url http://dx.doi.org/10.1155/2018/8928761
work_keys_str_mv AT zhenzhenliu addingarate1thirddimensiontoparallelconcatenatedsystematicpolarcode3dpolarcode
AT kainiu addingarate1thirddimensiontoparallelconcatenatedsystematicpolarcode3dpolarcode
AT chaodong addingarate1thirddimensiontoparallelconcatenatedsystematicpolarcode3dpolarcode
AT jiarulin addingarate1thirddimensiontoparallelconcatenatedsystematicpolarcode3dpolarcode
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