Noise measurement in high-speed domino pseudo-CMOS keeper
Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The pr...
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doaj-282d79a7547c410a880f32940568630e2021-02-03T14:04:10ZengSAGE PublishingMeasurement + Control0020-29402019-01-015210.1177/0020294018813642Noise measurement in high-speed domino pseudo-CMOS keeperR Jaikumar0P Poongodi1Department of ECE, RVS College of Engineering and Technology, Coimbatore, IndiaDepartment of ECE, Kalaignar Karunanidhi Institute of Technology, Coimbatore, IndiaNoise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.https://doi.org/10.1177/0020294018813642 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
R Jaikumar P Poongodi |
spellingShingle |
R Jaikumar P Poongodi Noise measurement in high-speed domino pseudo-CMOS keeper Measurement + Control |
author_facet |
R Jaikumar P Poongodi |
author_sort |
R Jaikumar |
title |
Noise measurement in high-speed domino pseudo-CMOS keeper |
title_short |
Noise measurement in high-speed domino pseudo-CMOS keeper |
title_full |
Noise measurement in high-speed domino pseudo-CMOS keeper |
title_fullStr |
Noise measurement in high-speed domino pseudo-CMOS keeper |
title_full_unstemmed |
Noise measurement in high-speed domino pseudo-CMOS keeper |
title_sort |
noise measurement in high-speed domino pseudo-cmos keeper |
publisher |
SAGE Publishing |
series |
Measurement + Control |
issn |
0020-2940 |
publishDate |
2019-01-01 |
description |
Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods. |
url |
https://doi.org/10.1177/0020294018813642 |
work_keys_str_mv |
AT rjaikumar noisemeasurementinhighspeeddominopseudocmoskeeper AT ppoongodi noisemeasurementinhighspeeddominopseudocmoskeeper |
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