VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

• Main Authors: Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu (Andy) Wu
• Format: Article
• Language: English
• Published: SpringerOpen 2003-12-01
• Series: EURASIP Journal on Advances in Signal Processing
• Subjects: cached FFT; mixed-scaling and rotation CORDIC; and OFDM communications.
• Online Access: http://dx.doi.org/10.1155/S1110865703309060

The technique of {orthogonal frequency division multiplexing (OFDM)} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT)} and {inverse FFT (IFFT)} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE)} based on the {{coordinate} rotation digital computer (CORDIC)} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048)-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K), DAB, and 2K-mode DVB.