Design and Simulation of a Nanoscale Threshold-Logic Multiplier
Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high spe...
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UIKTEN
2019-05-01
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| Series: | TEM Journal |
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| Online Access: | http://www.temjournal.com/content/82/TEMJournalMay2019_333_338.pdf |
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doaj-36c63cedc80740f792ccf69244f791f02020-11-25T02:34:03ZengUIKTENTEM Journal2217-83092217-83332019-05-018233333810.18421/TEM82-03Design and Simulation of a Nanoscale Threshold-Logic MultiplierMawahib Hussein SuliemanMariam MahmoudRemonda RaafatGehad RedaMultiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product.http://www.temjournal.com/content/82/TEMJournalMay2019_333_338.pdfMultiplieradderThreshold logic gates |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Mawahib Hussein Sulieman Mariam Mahmoud Remonda Raafat Gehad Reda |
| spellingShingle |
Mawahib Hussein Sulieman Mariam Mahmoud Remonda Raafat Gehad Reda Design and Simulation of a Nanoscale Threshold-Logic Multiplier TEM Journal Multiplier adder Threshold logic gates |
| author_facet |
Mawahib Hussein Sulieman Mariam Mahmoud Remonda Raafat Gehad Reda |
| author_sort |
Mawahib Hussein Sulieman |
| title |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier |
| title_short |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier |
| title_full |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier |
| title_fullStr |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier |
| title_full_unstemmed |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier |
| title_sort |
design and simulation of a nanoscale threshold-logic multiplier |
| publisher |
UIKTEN |
| series |
TEM Journal |
| issn |
2217-8309 2217-8333 |
| publishDate |
2019-05-01 |
| description |
Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product. |
| topic |
Multiplier adder Threshold logic gates |
| url |
http://www.temjournal.com/content/82/TEMJournalMay2019_333_338.pdf |
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AT mawahibhusseinsulieman designandsimulationofananoscalethresholdlogicmultiplier AT mariammahmoud designandsimulationofananoscalethresholdlogicmultiplier AT remondaraafat designandsimulationofananoscalethresholdlogicmultiplier AT gehadreda designandsimulationofananoscalethresholdlogicmultiplier |
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