Model-Based Design for Software Defined Radio on an FPGA
This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A tradition...
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doaj-38966228c80644a281f459b577099ee72021-03-29T20:03:31ZengIEEEIEEE Access2169-35362017-01-0158276828310.1109/ACCESS.2017.26927647895173Model-Based Design for Software Defined Radio on an FPGAXin Cai0Mingda Zhou1Xinming Huang2https://orcid.org/0000-0003-0584-3448State Key Laboratory of ISN, School of Telecommunications Engineering, Xidian University, Xi’an, Shaanxi, ChinaDepartment of Electrical and Computer Engineering, Worcester Polytechnic Institute, Worcester, MA, USADepartment of Electrical and Computer Engineering, Worcester Polytechnic Institute, Worcester, MA, USAThis paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency.https://ieeexplore.ieee.org/document/7895173/Software defined radioFPGAconvolutional codeViterbi decodersynchronization |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Xin Cai Mingda Zhou Xinming Huang |
spellingShingle |
Xin Cai Mingda Zhou Xinming Huang Model-Based Design for Software Defined Radio on an FPGA IEEE Access Software defined radio FPGA convolutional code Viterbi decoder synchronization |
author_facet |
Xin Cai Mingda Zhou Xinming Huang |
author_sort |
Xin Cai |
title |
Model-Based Design for Software Defined Radio on an FPGA |
title_short |
Model-Based Design for Software Defined Radio on an FPGA |
title_full |
Model-Based Design for Software Defined Radio on an FPGA |
title_fullStr |
Model-Based Design for Software Defined Radio on an FPGA |
title_full_unstemmed |
Model-Based Design for Software Defined Radio on an FPGA |
title_sort |
model-based design for software defined radio on an fpga |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2017-01-01 |
description |
This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency. |
topic |
Software defined radio FPGA convolutional code Viterbi decoder synchronization |
url |
https://ieeexplore.ieee.org/document/7895173/ |
work_keys_str_mv |
AT xincai modelbaseddesignforsoftwaredefinedradioonanfpga AT mingdazhou modelbaseddesignforsoftwaredefinedradioonanfpga AT xinminghuang modelbaseddesignforsoftwaredefinedradioonanfpga |
_version_ |
1724195391724847104 |