An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture
Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in...
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doaj-3b3efe1bcbf94cbcbd25a0bc4a953dde2021-03-11T00:06:12ZengMDPI AGMicromachines2072-666X2021-03-011229229210.3390/mi12030292An Ultra-Low-Power Embedded Processor with Variable Micro-ArchitectureWenheng Ma0Qiao Cheng1Yudi Gao2Lan Xu3Ningmei Yu4Faculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, ChinaFaculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, ChinaFaculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, ChinaFaculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, ChinaFaculty of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, ChinaEmbedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.https://www.mdpi.com/2072-666X/12/3/292ultra-low-powerembedded processorenergy efficiencyvariable micro-architecturepipeline register |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Wenheng Ma Qiao Cheng Yudi Gao Lan Xu Ningmei Yu |
spellingShingle |
Wenheng Ma Qiao Cheng Yudi Gao Lan Xu Ningmei Yu An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture Micromachines ultra-low-power embedded processor energy efficiency variable micro-architecture pipeline register |
author_facet |
Wenheng Ma Qiao Cheng Yudi Gao Lan Xu Ningmei Yu |
author_sort |
Wenheng Ma |
title |
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture |
title_short |
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture |
title_full |
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture |
title_fullStr |
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture |
title_full_unstemmed |
An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture |
title_sort |
ultra-low-power embedded processor with variable micro-architecture |
publisher |
MDPI AG |
series |
Micromachines |
issn |
2072-666X |
publishDate |
2021-03-01 |
description |
Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode. |
topic |
ultra-low-power embedded processor energy efficiency variable micro-architecture pipeline register |
url |
https://www.mdpi.com/2072-666X/12/3/292 |
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