Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. Thi...

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Main Authors: Sharad Sinha, Thambipillai Srikanthan
Format: Article
Language:English
Published: Hindawi Limited 2014-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2014/564924
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spelling doaj-3e071430cf8a4375b7bfbd9a3bd86b1c2020-11-25T00:49:54ZengHindawi LimitedInternational Journal of Reconfigurable Computing1687-71951687-72092014-01-01201410.1155/2014/564924564924Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level SynthesisSharad Sinha0Thambipillai Srikanthan1School of Computer Engineering, Nanyang Technological University, 639798, SingaporeSchool of Computer Engineering, Nanyang Technological University, 639798, SingaporeMultiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.http://dx.doi.org/10.1155/2014/564924
collection DOAJ
language English
format Article
sources DOAJ
author Sharad Sinha
Thambipillai Srikanthan
spellingShingle Sharad Sinha
Thambipillai Srikanthan
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
International Journal of Reconfigurable Computing
author_facet Sharad Sinha
Thambipillai Srikanthan
author_sort Sharad Sinha
title Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
title_short Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
title_full Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
title_fullStr Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
title_full_unstemmed Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
title_sort architecture and application-aware management of complexity of mapping multiplication to fpga dsp blocks in high level synthesis
publisher Hindawi Limited
series International Journal of Reconfigurable Computing
issn 1687-7195
1687-7209
publishDate 2014-01-01
description Multiplication is a common operation in many applications and there exist various types of multiplication operations. Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources. This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations. This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori. A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed. This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs. Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.
url http://dx.doi.org/10.1155/2014/564924
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AT thambipillaisrikanthan architectureandapplicationawaremanagementofcomplexityofmappingmultiplicationtofpgadspblocksinhighlevelsynthesis
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