A Full X-Band Phased-Array Transmit/Receive Module Chip in 65-nm CMOS Technology

• Main Authors: Hyohyun Nam, Van-Viet Nguyen, Van-Son Trinh, Jeong-Moon Song, Bok-Hyung Lee, Jung-Dong Park
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: CMOS; phased arrays; phase shifter; transceivers; wideband
• Online Access: https://ieeexplore.ieee.org/document/9069961/

In this paper, we present a phased-array transceiver chip operating in full X-band (8-12 GHz) in 65-nm CMOS technology. The presented transceiver for the transmit/receive module (TRM) consists of a 6-bit passive phase shifter, a 6-bit attenuator, a bi-directional gain amplifier (BDGA), and a single pole double throw (SPDT) switch connected to the internal power amplifier (PA) and the low-noise amplifier (LNA) to serve as a duplexer. A 64-bit SPI scan-chain is integrated for digital TRM control. The transmitter achieves greater than 15 dB of power gain with 11.84 dBm at the output 1-dB compression point (OP1dB). To achieve a wideband operation of the passive phase shifter, we assigned two different resonant frequencies for the phase leading and lagging networks and aligned the slopes of their phase responses to have the desired phase shifts at the center frequency. The RMS phase error is less than 5°, and the RMS amplitude error is less than 0.45 dB for all phase and attenuation states within 8-12 GHz while dissipating 216 mW dc power from a 1 V power supply. The receiver shows greater than 15 dB of power gain and has a noise figure (NF) of less than 8.4 dB for the entire X-band. The RMS phase error and the RMS amplitude error are less than 5° and 0.45 dB, respectively, for all control states within 8-12 GHz. The receiver consumes 110 mW with a 1 V power supply. The transceiver chip occupies an area of $4\times1.88$ mm².