Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory
This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided...
Main Authors: | Jia-Wei Lee, Meng-Hsueh Chiang |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
|
Series: | IEEE Journal of the Electron Devices Society |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9137335/ |
Similar Items
-
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions
by: Ying-Chen Chen, et al.
Published: (2021-01-01) -
Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing
by: Tommaso Zanotti, et al.
Published: (2020-01-01) -
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates
by: Xiaole Cui, et al.
Published: (2021-01-01) -
Optimisation technologique et caractérisation électrique de mémoires résistives OxRRAM pour applications basse consommation
by: Cabout, Thomas
Published: (2014) -
Enhancing the Electrical Uniformity and Reliability of the HfO<sub>2</sub>-Based RRAM Using High-Permittivity Ta<sub>2</sub>O<sub>5</sub> Side Wall
by: Mei Yuan, et al.
Published: (2018-01-01)