FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field
Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed,...
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doaj-4a7cce683016450f987b43701721cfd12021-03-29T21:59:08ZengIEEEIEEE Access2169-35362019-01-01717881117882610.1109/ACCESS.2019.29584918928563FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime FieldMd. Mainul Islam0https://orcid.org/0000-0002-9686-5994Md. Selim Hossain1https://orcid.org/0000-0003-3754-3618Moh. Khalid Hasan2https://orcid.org/0000-0002-7773-3523Md. Shahjalal3https://orcid.org/0000-0002-4876-6860Yeong Min Jang4https://orcid.org/0000-0003-1487-086XDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electrical and Electronic Engineering, Khulna University of Engineering and Technology, Khulna, BangladeshDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDeveloping a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.https://ieeexplore.ieee.org/document/8928563/Elliptic curve cryptography (ECC)elliptic curve point multiplication (ECPM)twisted Edwards curveside-channel attacks (SCAs)field-programmable gate array (FPGA) |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Md. Mainul Islam Md. Selim Hossain Moh. Khalid Hasan Md. Shahjalal Yeong Min Jang |
spellingShingle |
Md. Mainul Islam Md. Selim Hossain Moh. Khalid Hasan Md. Shahjalal Yeong Min Jang FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field IEEE Access Elliptic curve cryptography (ECC) elliptic curve point multiplication (ECPM) twisted Edwards curve side-channel attacks (SCAs) field-programmable gate array (FPGA) |
author_facet |
Md. Mainul Islam Md. Selim Hossain Moh. Khalid Hasan Md. Shahjalal Yeong Min Jang |
author_sort |
Md. Mainul Islam |
title |
FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field |
title_short |
FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field |
title_full |
FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field |
title_fullStr |
FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field |
title_full_unstemmed |
FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field |
title_sort |
fpga implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2019-01-01 |
description |
Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level. |
topic |
Elliptic curve cryptography (ECC) elliptic curve point multiplication (ECPM) twisted Edwards curve side-channel attacks (SCAs) field-programmable gate array (FPGA) |
url |
https://ieeexplore.ieee.org/document/8928563/ |
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