Design of Linear Systolic Arrays for Matrix Multiplication
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed...
Main Authors: | , , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Stefan cel Mare University of Suceava
2014-02-01
|
Series: | Advances in Electrical and Computer Engineering |
Subjects: | |
Online Access: | http://dx.doi.org/10.4316/AECE.2014.01006 |
id |
doaj-4c055b9fc1354e88bb18fd5bc3d50be6 |
---|---|
record_format |
Article |
spelling |
doaj-4c055b9fc1354e88bb18fd5bc3d50be62020-11-25T00:40:59ZengStefan cel Mare University of SuceavaAdvances in Electrical and Computer Engineering1582-74451844-76002014-02-01141374210.4316/AECE.2014.01006Design of Linear Systolic Arrays for Matrix MultiplicationMILOVANOVIC, E. I.STOJCEV, M. K.MILOVANOVIC, I. Z.NIKOLIC, T. R. This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.http://dx.doi.org/10.4316/AECE.2014.01006address generator unitslinear systolic arraysmatrix multiplication |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
MILOVANOVIC, E. I. STOJCEV, M. K. MILOVANOVIC, I. Z. NIKOLIC, T. R. |
spellingShingle |
MILOVANOVIC, E. I. STOJCEV, M. K. MILOVANOVIC, I. Z. NIKOLIC, T. R. Design of Linear Systolic Arrays for Matrix Multiplication Advances in Electrical and Computer Engineering address generator units linear systolic arrays matrix multiplication |
author_facet |
MILOVANOVIC, E. I. STOJCEV, M. K. MILOVANOVIC, I. Z. NIKOLIC, T. R. |
author_sort |
MILOVANOVIC, E. I. |
title |
Design of Linear Systolic Arrays for Matrix Multiplication |
title_short |
Design of Linear Systolic Arrays for Matrix Multiplication |
title_full |
Design of Linear Systolic Arrays for Matrix Multiplication |
title_fullStr |
Design of Linear Systolic Arrays for Matrix Multiplication |
title_full_unstemmed |
Design of Linear Systolic Arrays for Matrix Multiplication |
title_sort |
design of linear systolic arrays for matrix multiplication |
publisher |
Stefan cel Mare University of Suceava |
series |
Advances in Electrical and Computer Engineering |
issn |
1582-7445 1844-7600 |
publishDate |
2014-02-01 |
description |
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator
unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware
accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both
the computation and communication by employing hardware address generator units (AGUs). The proposed design
has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed
solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing
elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware
overhead of 0.6% for 32-bit PEs. |
topic |
address generator units linear systolic arrays matrix multiplication |
url |
http://dx.doi.org/10.4316/AECE.2014.01006 |
work_keys_str_mv |
AT milovanovicei designoflinearsystolicarraysformatrixmultiplication AT stojcevmk designoflinearsystolicarraysformatrixmultiplication AT milovanoviciz designoflinearsystolicarraysformatrixmultiplication AT nikolictr designoflinearsystolicarraysformatrixmultiplication |
_version_ |
1725287828105986048 |