Design of Linear Systolic Arrays for Matrix Multiplication
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Stefan cel Mare University of Suceava
2014-02-01
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| Series: | Advances in Electrical and Computer Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.4316/AECE.2014.01006 |