Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow
Abstract A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor base...
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Online Access: | https://doi.org/10.1049/cdt2.12032 |
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doaj-4ec0230edea444cd87fa2f0e26033add2021-10-07T06:06:58ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-11-0115640942610.1049/cdt2.12032Introducing KeyRing self‐timed microarchitecture and timing‐driven design flowMickael Fiorentino0Claude Thibeault1Yvon Savaria2Department of Electrical Engineering Polytechnique Montreal Montreal Quebec CanadaDepartment of Electrical Engineering Ecole de Technologie Superieure Montreal Quebec CanadaDepartment of Electrical Engineering Polytechnique Montreal Montreal Quebec CanadaAbstract A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating.https://doi.org/10.1049/cdt2.12032 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Mickael Fiorentino Claude Thibeault Yvon Savaria |
spellingShingle |
Mickael Fiorentino Claude Thibeault Yvon Savaria Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow IET Computers & Digital Techniques |
author_facet |
Mickael Fiorentino Claude Thibeault Yvon Savaria |
author_sort |
Mickael Fiorentino |
title |
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow |
title_short |
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow |
title_full |
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow |
title_fullStr |
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow |
title_full_unstemmed |
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow |
title_sort |
introducing keyring self‐timed microarchitecture and timing‐driven design flow |
publisher |
Wiley |
series |
IET Computers & Digital Techniques |
issn |
1751-8601 1751-861X |
publishDate |
2021-11-01 |
description |
Abstract A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating. |
url |
https://doi.org/10.1049/cdt2.12032 |
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