| Summary: | The task of creating a testbench for functional verification is considered. This verification process establishes the reconvergence (equivalence) of the device specification and the register-transfer level (RTL) model - a logical network which was built in the synthesis process. In the UVM methodology, usually used in the modern design of digital devices for functional verification, a testing strategy, that determines the way in which a test case is constructed, is the random selection of space-driven constrained-random transaction-level self-checking testbenches. The rules and recommendations of UVM contain a standardized structure of the test bench, which is oriented towards the development of transformational devices. For the case where the model of the design is a behavior algorithm, it is proposed to build a testbench as a model of the environment of the design presented in the language of PRALU. The environment model of the developed device allows to avoid situations when the device under test is verified with sufficient coverage, but in an incomplete environment. The environment model on PRALU can be automatically converted into a transaction level model to develop a testbench in the simulator environment of the hardware description language.
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