DESIGN AND IMPLEMENTATION OF HIGH SPEED LATCHED COMPARATOR USING gm/Id SIZING METHOD
Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is de...
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2017-01-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_2_Iss_4_Paper_2_300_304.pdf |
| Summary: | Design of an analog circuit depends on several factors such as design
methodology, good modeling and technology characterization. This work
focuses on designing a high speed (1.6GHz) latched comparator with low
power consumption suitable for ADCs in SoC applications. The latched
comparator is designed with StrongArm latch as the primary decision
and amplification stage followed by a latching element to drive the output
load. The StrongArm latch is a proven circuit topology suitable for all
seasons. The zero static power consumption of StrongArm latch is
exploited to design a low power comparator. The output latch is used to
hold the previous output value during the tracking time of the
comparator. The designed comparator achieves zero setup time at a clock
frequency of 1.6GHz and produces digital output with a maximum delay
of 180ps.The comparator is implemented with SAED 32nm technology
libraries. The performance has been analyzed using HSPICE simulator. |
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| ISSN: | 2395-1672 2395-1680 |