DESIGN AND IMPLEMENTATION OF HIGH SPEED LATCHED COMPARATOR USING gm/Id SIZING METHOD
Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is de...
Main Author: | S. Ramasamy |
---|---|
Format: | Article |
Language: | English |
Published: |
ICT Academy of Tamil Nadu
2017-01-01
|
Series: | ICTACT Journal on Microelectronics |
Subjects: | |
Online Access: | http://ictactjournals.in/paper/IJME_Vol_2_Iss_4_Paper_2_300_304.pdf |
Similar Items
-
Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator
by: Ning Chen, et al.
Published: (2020-12-01) -
An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications
by: Vikrant Varshney, et al.
Published: (2019-01-01) -
Validación al castellano de una escala de evaluación de la lactancia materna: el LATCH. Análisis de fiabilidad Validation of the LATCH assessment tool into Spanish: Reliability analysis
by: Carmen Báez León, et al.
Published: (2008-09-01) -
Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique
by: Vijay G Savani, et al.
Published: (2017-02-01) -
An Offset Cancelation Technique for Latch Type Sense Amplifiers
by: G. Souliotis, et al.
Published: (2014-12-01)