Low Cost Test Pattern Generation in Scan-Based BIST Schemes

Low Cost Test Pattern Generation in Scan-Based BIST Schemes

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input c...

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Bibliographic Details
Main Authors: Guohe Zhang, Ye Yuan, Feng Liang, Sufen Wei, Cheng-Fu Yang
Format: Article
Language:English
Published: MDPI AG 2019-03-01
Series:Electronics
Subjects:
test pattern generation
built-in self-test
broadcast circuit
low cost
Online Access:http://www.mdpi.com/2079-9292/8/3/314
Description
Summary:This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.
ISSN:2079-9292

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