Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes
Spiking neural networks (SNNs) are the third generation of neural networks and can explore both rate and temporal coding for energy-efficient event-driven computation. However, the decision accuracy of existing SNN designs is contingent upon processing a large number of spikes over a long period. Ne...
Main Authors: | , , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Frontiers Media S.A.
2020-02-01
|
Series: | Frontiers in Neuroscience |
Subjects: | |
Online Access: | https://www.frontiersin.org/article/10.3389/fnins.2020.00104/full |
id |
doaj-5ff28c8b84c04b60a79a475847c40e8e |
---|---|
record_format |
Article |
spelling |
doaj-5ff28c8b84c04b60a79a475847c40e8e2020-11-25T02:17:43ZengFrontiers Media S.A.Frontiers in Neuroscience1662-453X2020-02-011410.3389/fnins.2020.00104498784Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike CodesChangqing Xu0Wenrui Zhang1Yu Liu2Peng Li3School of Microelectronics, Xidian University, Xi'an, ChinaDepartment of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA, United StatesDepartment of Electrical and Computer Engineering, Texas A&M University, College Station, TX, United StatesDepartment of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA, United StatesSpiking neural networks (SNNs) are the third generation of neural networks and can explore both rate and temporal coding for energy-efficient event-driven computation. However, the decision accuracy of existing SNN designs is contingent upon processing a large number of spikes over a long period. Nevertheless, the switching power of SNN hardware accelerators is proportional to the number of spikes processed while the length of spike trains limits throughput and static power efficiency. This paper presents the first study on developing temporal compression to significantly boost throughput and reduce energy dissipation of digital hardware SNN accelerators while being applicable to multiple spike codes. The proposed compression architectures consist of low-cost input spike compression units, novel input-and-output-weighted spiking neurons, and reconfigurable time constant scaling to support large and flexible time compression ratios. Our compression architectures can be transparently applied to any given pre-designed SNNs employing either rate or temporal codes while incurring minimal modification of the neural models, learning algorithms, and hardware design. Using spiking speech and image recognition datasets, we demonstrate the feasibility of supporting large time compression ratios of up to 16×, delivering up to 15.93×, 13.88×, and 86.21× improvements in throughput, energy dissipation, the tradeoffs between hardware area, runtime, energy, and classification accuracy, respectively based on different spike codes on a Xilinx Zynq-7000 FPGA. These results are achieved while incurring little extra hardware overhead.https://www.frontiersin.org/article/10.3389/fnins.2020.00104/fulltime compressionspiking neural networksinput-output-weighted spiking neuronstime averagingliquid-state machine |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Changqing Xu Wenrui Zhang Yu Liu Peng Li |
spellingShingle |
Changqing Xu Wenrui Zhang Yu Liu Peng Li Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes Frontiers in Neuroscience time compression spiking neural networks input-output-weighted spiking neurons time averaging liquid-state machine |
author_facet |
Changqing Xu Wenrui Zhang Yu Liu Peng Li |
author_sort |
Changqing Xu |
title |
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes |
title_short |
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes |
title_full |
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes |
title_fullStr |
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes |
title_full_unstemmed |
Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes |
title_sort |
boosting throughput and efficiency of hardware spiking neural accelerators using time compression supporting multiple spike codes |
publisher |
Frontiers Media S.A. |
series |
Frontiers in Neuroscience |
issn |
1662-453X |
publishDate |
2020-02-01 |
description |
Spiking neural networks (SNNs) are the third generation of neural networks and can explore both rate and temporal coding for energy-efficient event-driven computation. However, the decision accuracy of existing SNN designs is contingent upon processing a large number of spikes over a long period. Nevertheless, the switching power of SNN hardware accelerators is proportional to the number of spikes processed while the length of spike trains limits throughput and static power efficiency. This paper presents the first study on developing temporal compression to significantly boost throughput and reduce energy dissipation of digital hardware SNN accelerators while being applicable to multiple spike codes. The proposed compression architectures consist of low-cost input spike compression units, novel input-and-output-weighted spiking neurons, and reconfigurable time constant scaling to support large and flexible time compression ratios. Our compression architectures can be transparently applied to any given pre-designed SNNs employing either rate or temporal codes while incurring minimal modification of the neural models, learning algorithms, and hardware design. Using spiking speech and image recognition datasets, we demonstrate the feasibility of supporting large time compression ratios of up to 16×, delivering up to 15.93×, 13.88×, and 86.21× improvements in throughput, energy dissipation, the tradeoffs between hardware area, runtime, energy, and classification accuracy, respectively based on different spike codes on a Xilinx Zynq-7000 FPGA. These results are achieved while incurring little extra hardware overhead. |
topic |
time compression spiking neural networks input-output-weighted spiking neurons time averaging liquid-state machine |
url |
https://www.frontiersin.org/article/10.3389/fnins.2020.00104/full |
work_keys_str_mv |
AT changqingxu boostingthroughputandefficiencyofhardwarespikingneuralacceleratorsusingtimecompressionsupportingmultiplespikecodes AT wenruizhang boostingthroughputandefficiencyofhardwarespikingneuralacceleratorsusingtimecompressionsupportingmultiplespikecodes AT yuliu boostingthroughputandefficiencyofhardwarespikingneuralacceleratorsusingtimecompressionsupportingmultiplespikecodes AT pengli boostingthroughputandefficiencyofhardwarespikingneuralacceleratorsusingtimecompressionsupportingmultiplespikecodes |
_version_ |
1724885617876140032 |