Design Of A 65 Nm Cmos Comparator With Hysteresis
<p class="14AbstracttekstasAbstract"><span lang="EN-GB">The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually opera...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Vilnius Gediminas Technical University
2014-05-01
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| Series: | Mokslas: Lietuvos Ateitis |
| Subjects: | |
| Online Access: | http://www.mla.vgtu.lt/index.php/mla/article/view/640 |
| Summary: | <p class="14AbstracttekstasAbstract"><span lang="EN-GB">The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC.</span></p> |
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| ISSN: | 2029-2341 2029-2252 |