| Summary: | In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>α</mi></semantics></math></inline-formula> being in the range <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>[</mo><mo>−</mo><mi>n</mi><mo>,</mo><mi>n</mi><mo>]</mo></mrow></semantics></math></inline-formula>, where <i>n</i> is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>α</mi><mi>seed</mi></msub></semantics></math></inline-formula> as passive elements results in the design of a series of 51 FOEs with different <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>α</mi></semantics></math></inline-formula> being in the range <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>[</mo><mo>−</mo><mn>2</mn><mo>,</mo><mn>2</mn><mo>]</mo></mrow></semantics></math></inline-formula> that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 <inline-formula>μ<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept.
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