Design Options for Current Limit and Power Limit Circuit Protections for LDOs

• Main Authors: PLESA, C.-S., DIMITRIU, B., NEAG, M.
• Format: Article
• Language: English
• Published: Stefan cel Mare University of Suceava 2019-02-01
• Series: Advances in Electrical and Computer Engineering
• Subjects: current limiters; power dissipation; power system protection; short-circuit currents; thermal analysis
• Online Access: http://dx.doi.org/10.4316/AECE.2019.01008
• ISSN: 1582-7445; 1844-7600

This paper presents novel circuitry for protection of the power transistor in LDOs with adjustable output voltage implemented in BJT technologies. First, an improvement is proposed to a current limit circuit reported previously, that significantly reduces the variation of the value the output current is limited to, caused by setting the output voltage to different values. Next, two circuits for ensuring that the power transistor operates within its safe operating area are introduced; they are based on the proposed current limit circuit, but its activation point is no longer proportional to the output current but to the sum of the output current and a current proportional to the voltage drop across the power transistor. Finally, a circuit that monitors and limits the power dissipated is described; it also employs the proposed current limit circuit but this time the activation point is proportional to the product of the output current and the voltage drop across the power transistor. Three LDOs that employ the three types of protections proposed here are then compared, considering the power dissipated by the power transistor and the resulting maximum die temperature.