Immunity Characterization of FPGA I/Os for Fault-Tolerant Circuit Designs against EMI

• Main Authors: NGUYEN, V. T., DAM, M. T., SO, J., LEE, J.-G.
• Format: Article
• Language: English
• Published: Stefan cel Mare University of Suceava 2019-05-01
• Series: Advances in Electrical and Computer Engineering
• Subjects: immunity; susceptibility; integrated circuit; electromagnetic compatibility; electromagnetic interference
• Online Access: http://dx.doi.org/10.4316/AECE.2019.02005

This paper characterizes the immunity of I/Os under different supply voltages for fault-tolerant circuit designs against electromagnetic interference. The direct power injection approach is used as a means to characterize the immunity of circuits. In this work, the immunity characterization has been performed under two scenarios: (1) an input buffer of a Field Programmable Gate Array (FPGA) followed by a single flip-flop, and (2) the FPGA input buffer followed by a redundancy-based fault-tolerant circuit. The experimental results show that when downscaling the supply voltage through a set of nominal values (i.e., 3.3, 2.5, 1.8, 1.5, 1.2 V), the immunity of I/Os is decreased from the highest level at 3.3 V to the lowest at 1.2 V. Particularly, the maximum difference in the immunity is about 16.8 dB at the frequency of 600 MHz. Moreover, experiments demonstrate that I/O buffers followed by the redundancy-based fault-tolerant circuit can improve the immunity of the circuit up to 4 dB below the frequency band of 400 MHz. Thus, the redundancy-based fault-tolerant circuit can support I/Os to operate reliably in the harsh environment.