| Summary: | This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm<sup>2</sup>, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.
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